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| this is information on a product in full production. june 2013 docid024387 rev 2 1/98 98 stlux385a digital controller for lighting and power conversion applications with 6 programmable pwm generators, 96 mhz pll, dali datasheet - production data features ? 6 programmable pwm generators (smeds) (state machine event driven) ? 10 ns event detection and reaction ? max.1.3 ns pwm resolution ? single, coupled and two-coupled operational modes ? up to 3 internal/external events per smed ? dali (digital addressable lighting interface) ? interrupt driven hardware encoder ? bus frequency: 1.2, 2.4 or 4.8 khz ? iec 60929 and iec 62386 compliant plus 24-bit frame extension ? configurable noise rejection filter ? reverse polarity on tx/rx lines ? 4 analog comparators ? 4 internal 4-bit references ? 1 external reference ? less than 50 ns propagation time ? continuous comparison cycle ? 8 analog-to-digital converters (adc) ? 10-bit precision, with operational amplifier to extend resolution to 12-bit equivalent ? sequencer functionality ? input impedance: 1 m ? configurable gain value: x1 or x 4 ? integrated microcontroller ? advanced stm8 core with harvard architecture and 3-stage pipeline ?max. f cpu : 16 mhz ? memories ? flash and e 2 prom with read while write (rww) and error correction code (ecc) ? program memory: 32 kbytes flash; data retention 15 years at 85 c after 10 kcycles at 25 c ? data memory: 1 kbyte true data e 2 prom; data retention:15 years at 85 c after 100 kcycles at 85 c ? ram: 2 kbytes ? rom: 2 kbytes ? clock management ? internal 96 mhz pll ? low-power oscillator circuit for external crystal resonator or direct clock input ? internal, user-trimmable 16 mhz rc and low-power 153.6 khz rc oscillators ? clock security system with clock monitor ? basic peripherals ? system and auxiliary timers ? iwdg/wwdg watchdog, awu, itc ? reset and supply management ? multiple low-power modes (wait, slow, auto- wakeup, halt) with user definable clock gating ? low consumption power-on and power- down reset ? i/o ? 12 multi-function bidirectional gpio with highly robust design, immune against current injection ? 6 fast digital input digin, with configurable pull-up ? communication interfaces ? uart asynchronous with sw flow-control ?i 2 c master/slave fast-slow speed rate ? operating temperature ? -40 c up to 105 c tssop38 www.st.com
contents stlux385a 2/98 docid024387 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 introducing smed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 smed (state machine event driven): configurable pwm generator . . . . . . 9 3.1.1 smed coupling schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 connection matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 internal controller (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.4 single wire interface module (swim) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.5 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 basic peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 flash program and data e 2 prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.2 write protection (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.3 protection of user boot code (ubc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.4 read-out protection (rop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5.1 internal 16 mhz rc oscillator (hsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5.2 internal 153.6 khz rc oscillator (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5.3 internal 96 mhz pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5.4 external clock input/crystal oscillator (hse) . . . . . . . . . . . . . . . . . . . . . 18 3.6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.1 digital addressable lighting interface (dali) . . . . . . . . . . . . . . . . . . . . . 19 docid024387 rev 2 3/98 stlux385a contents 3.7.2 universal asynchronous receiver/transmitter (uart) . . . . . . . . . . . . . . 20 3.7.3 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 i/o multifunction signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 multifunction configuration policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 port p0 i/o multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 26 5.2.1 alternate function p0 configuration signals . . . . . . . . . . . . . . . . . . . . . . 27 5.2.2 port p0 diagnostic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 port p0 i/o functional multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.4 p0 programmable pull-up and speed feature . . . . . . . . . . . . . . . . . . . . 28 5.3 port p1 i/o multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 28 5.3.1 port p1 i/o multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.2 p1 programmable pull-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 port p2 i/o multifunction configuration signal . . . . . . . . . . . . . . . . . . . . . 30 5.4.1 p2 programmable pull-up feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 multifunction port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 memory map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 general purpose i/o gpio0 register map . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.2 general purpose i/o gpio1 register map . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.3 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2.4 flash and e 2 prom non-volatile memories . . . . . . . . . . . . . . . . . . . . . . 37 6.2.5 reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.6 clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2.7 wwdg timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2.8 iwdg timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2.9 awu timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 contents stlux385a 4/98 docid024387 rev 2 6.2.10 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2.11 universal asynchronous receiver/transmitter (uart) . . . . . . . . . . . . . . 42 6.2.12 system timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2.13 digital addressable lighting interface (dali) . . . . . . . . . . . . . . . . . . . . . 43 6.2.14 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2.15 state machine event driven (smeds) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2.16 cpu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.17 global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2.18 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2.19 swim control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 option byte register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2 option byte register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.1 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2 device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.4 typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.1.5 loading capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.1.6 pin output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.1 vout external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 77 10.3.4 internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 80 10.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 docid024387 rev 2 5/98 stlux385a contents 10.3.7 typical output curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.3.8 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.9 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.3.10 10-bit sar adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.3.11 analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.12 dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.4 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4.1 electrostatic discharge (esd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4.2 static latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13 stlux385a development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 list of tables stlux385a 6/98 docid024387 rev 2 list of tables table 1. connection matrix interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3. multifunction configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4. p0 internal multiplexing signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. port p1 i/o multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. port p2 i/o multiplexing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. internal memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. general purpose i/o gpio0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. general purpose i/o gpio0 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. miscellaneous direct register address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. miscellaneous indirect register address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. non-volatile memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. rst_sr register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. clock and clock controller register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. wwdg timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. iwdg timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. awu timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. uart register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. system timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. dali register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. adc register map and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 23. smed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 24. cpu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 25. cfg_gcr register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. interrupt software priority register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 27. swim register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 28. interrupt vector exception table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. option byte register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 30. unique id register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 31. dev id register overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 32. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 33. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 34. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 35. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 36. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. supply base current consumption at v dd /v dda = 3.3/5 v . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 38. supply low power consumption at v dd /v dda = 3.3/5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39. peripheral supply current consumption at v dd /v dda = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . 72 table 40. peripheral supply current consumption at v dd /v dda = 5 v . . . . . . . . . . . . . . . . . . . . . . . . 73 table 41. hse user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 table 42. hse crystal/ceramic resonator oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 table 43. hsi rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 44. lsi rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 45. pll internal source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 46. flash program memory/data e 2 prom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 47. voltage dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 48. current dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 docid024387 rev 2 7/98 stlux385a list of tables table 49. operating frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 50. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 51. i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 52. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 53. adc accuracy characteristics at v dd /v dda 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 54. adc accuracy characteristics at v dd /v dda 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55. analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 57. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 58. electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 59. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 60. tssop38 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 61. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 list of figures stlux385a 8/98 docid024387 rev 2 list of figures figure 1. stlux385a internal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. coupled smed overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. smed subsystem overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. flash and e 2 prom internal memory organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. tssop38 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. port p0 i/o functional multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. port p1 i/o multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 12. external capacitor cvout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 13. pwm current consumption with f smed =pll f pwm =0.5 mhz at v dd /v dda =3.3v . . . . . . . . 75 figure 14. pwm current consumption with f smed =pll f pwm =0.5 mhz at v dd /v dda =5v . . . . . . . . . . 75 figure 15. pwm current consumption with f smed =hsi f pwm =0.5 mhz at v dd /v dda =3.3v. . . . . . . . . 76 figure 16. pwm current consumption with f smed =hsi f pwm =0.5 mhz at v dd /v dda =5v . . . . . . . . . . 76 figure 17. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 18. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 19. tssop8 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 docid024387 rev 2 9/98 stlux385a description 1 description the stlux385a is part of the masterlux? family of st microelectronics digital devices tailored for lighting and power conversion. the stlux385a has been successfully integrated in a wide range of architectures and applications, starting from simple buck converters for led driving, boost for power factor correction, half-bridge resonant converters for dimmable led strings, up to full-bridge control in hid lamp ballasts, wireless power chargers and tv power supplies. 1.1 introducing smed the heart of the stlux385a is the smed (state machine event driven) technology which allows the device to operate six independently configurable pwm clocks with a maximum resolution of 1.3 ns. a smed is a powerful autonomous state machine, which is programmed to react to both external and internal events and may evolve without any software intervention. the smed reaction time can be as low as 10.4 ns, giving the stlux385a the ability of operating in time-critical applications. the smed offers superior performance when compared to traditional, timer based, pwm generators. each smed is configured via the stlux385a internal microcontroller. the integrated controller extends the stlux385a reliability and guarantees more than 15 years of both operating lifetime and memory data retention for program and data memory after cycling. a set of dedicated peripherals complete the stlux385a: ? 4 analog comparators with configurable references and 50 ns max. propagation delay. it is ideal to implement zero current detection algorithms or detect current peaks. ? 10-bit adc with configurable op-amp and 8 channel sequencer. ? dali: hardware interface that provides full iec 60929 and iec 62386 slave interface. ? 96 mhz pll for high output signal resolution. 1.2 documentation the following datasheet contains the description of features, pinout, pin assignment, electrical characteristics, mechanical data and ordering information. ? for information on programming, erasing and protection of the internal flash memory, please refer to the stm8 flash programming manual (pm0047). ? for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). system architecture stlux385a 10/98 docid024387 rev 2 2 system architecture the stlux385a generates and controls pwm signals by means of a state machine, called smed (state machine event driven). the following picture gives an overview of the internal architecture. figure 1. stlux385a internal design the core of the device is the smed unit: a hardware state machine driven by system events. the smed includes 4 states (s0, s1, s2 and s3) available during running operations. a special hold state is provided as well. the smed allows the user to configure, for every state, which system events trigger a transaction to a new state. during a transaction from one state to the other, the pwm output signal level can be updated. once a smed is configured and running, it becomes an autonomous unit, so no interaction is required since the snmed automatically reacts to system events. thanks to the smed's 96 mhz operating frequency and their automatic dithering function, the pwm maximum resolution is 1.3 ns. the stlux385a has 6 smeds available. multiple smeds can operate independently from each other or they can be grouped together to form a more powerful state machine. the stlux385a also integrates a low-power stm8 microcontroller which is used to configure and monitor the smed activity and to supply external communication such as dali. the stm8 controller has full access to all the stlux385a sub-systems, including the smeds. the stlux385a also features a sequential adc, which can be configured to continuously sample up to 8 channels. the following section illustrates the overall system block and shows how smeds have been implemented in the stlux385a architecture. docid024387 rev 2 11/98 stlux385a system architecture 2.1 block diagram figure 2. internal block diagram lsi int. oscillator hsi int. oscillator clock controller clock controller power management pll 96mhz reset control unit itc (interrupt ctrl ) awu (auto-wakeup) wwdg (win. watchdog) iwdg (ind. watchdog) gpio1 1kb e2prom data area 2kb ram 2kb rom bootrom system timer uart dali 6 digital input lines smed0 (pwm0) swim & dm (debug module) internal controller address and data bus i n t. b u s smed1 (pwm1) smed2 (pwm2) smed3 (pwm3) smed4 (pwm4) smed5 (pwm5) p 1 i o 32kb flash program area msc (misc. registers) mvr por resetcontroller mlvd lvd lvr dlvd d hse ext. oscillator gpio0 i 2 c 4 analog comparators connection box p 2 i o adc ? 8 channel p 0 i o product overview stlux385a 12/98 docid024387 rev 2 3 product overview this following section describes the features implemented in the product device. 3.1 smed (state machine event driven): configurable pwm generator the smed is an advanced programmable pwm generator signal. the smed (state machine event driven) is a state machine device controllable by both external events (primary i/o signals) and internal events (counter timers), which generate an output signal (pwm) depending on the evolution of the internal state machine. the pwm signal generated by the smed is therefore shaped by external events and not by a single timer. this mechanism allows controlled high frequency pwm signals to be generated. the smed is also autonomous: once it has been configured by the stlux385a internal controller, the smed can operate without any software interaction. stlux385a provides 6 smed units. multiple smeds can operate independently from each other or they can be grouped together to form a more powerful state machine. the main features of a smed are here below described: ? configurable state machine generating a pwm signal ? more than 10.4 ns pwm native resolution ? up to 1.3 ns pwm resolution when using smed dithering ? 6 states available in each smed: idle, s0, s1, s2, s3 plus a special hold state ? transactions triggered by synchronous and asynchronous external events or internal timer ? each transaction can generate an interrupt ? fifteen registers available to configure the state machine behavior ? four 16-bit configurable time registers, one for each running state (t0, t1, t2, t3) ? internal resources accessible through processor interface ? eight interrupt request lines 3.1.1 smed coupling schemes the smed coupling extends the capability of the single smed, preserving the independence of each fsm programmed state evolution. the coupling scheme allows the smed pulse signals to be interleaved on their own pwm or on a merged single pwm output. the stlux385a supports the following coupled configuration schemes: ? single smed configuration ? synchronous coupled smed ? asynchronous coupled smed ? synchronous two coupled smed ? asynchronous two coupled smed ? external controlled smed docid024387 rev 2 13/98 stlux385a product overview the smed units may be configured in different coupled schemes through the smdx_glbconf and smdx_drvout bit fields of msc_smedcfgxy registers. an outline of smed subsystem is shown in figure 3 . figure 3. coupled smed overview 3.1.2 connection matrix the connection matrix extends the input connectivity of each smed unit so that a smed can receive events from a wide range of sources. through the matrix, it's possible to connect the smed inputs to various signal families such as digital inputs, comparator output signals, sw events, and three pwm internal feedback signals as shown in figure 4 . the list of the available event sources is the following: ? digin(5:0) digital input lines ? cmp(3:0) analog comparator outputs ? pwm(5:0) output signals of smeds (only pwm 0, 1 and 5 are accessible) ? sw(5:0) software events smed0 smed1 smed2 smed3 pwm0 pwm1 pwm2 pwm3 pair1 pair2 smed4 smed5 pwm4 pwm5 pair3 gipc08051437fsr product overview stlux385a 14/98 docid024387 rev 2 the following image shows the connection matrix and signal interconnections as they are implemented in the stlux385a device. figure 4. smed subsystem overview connection matrix interconnection every smed unit has three input selection lines, one for each in_sig input, configurable via the msc_cboxs(5:0) register. the selection lines choose the interconnection between one of possible four connection matrix signals for each smed input event in_sig(y). the next table shows the layout of the connection matrix interconnection signals as implemented on the stlux385a. + - cp0 dac0 cpp[0] dac3 cmp3 + - cp1 + - cp2 + - cp3 dac1 cpp[1] dac2 cpp[2] cpp[3] sw[5:0] pwm0 pwm1 pwm5 digin[5:0] smed0 digital comparators insig00 insig01 insig02 pwm0 smed1 insig10 insig11 insig12 pwm1 smed2 iinsig20 insig21 pinsig22 pwm2 smed3 insig30 insig31 insig32 pwm3 smed4 insig40 insig41 insig42 pwm4 smed5 insig50 insig51 insig52 pwm5 c o n n e c t i o n m a t r i x gipc080520131443fsr docid024387 rev 2 15/98 stlux385a product overview connection matrix legend: ? x represents the smed[5:0] number ? y represents the smed input signal number (in_sig[2:0]) ? z represents the in_sig(y) selection signal note: each smed input has independent connection matrix selection signals. 3.2 internal controller (cpu) the stlux385a device integrates a programmable stm8 controller acting as a device supervisor. the stm8 is a modern cisc core and has been designed for code efficiency and performance. it contains 21 internal registers (six of them directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions. table 1. connection matrix interconnection conb_s(x)_(y)(z) smed number smed input smed input signal selection (z) (x) (y) 00 01 10 11 0 0 cp0 dig0 dig2 dig5 1 cp1 dig0 dig3 cp3 2 cp2 dig1 dig4 sw0 1 0 cp1 dig1 dig3 dig0 1 cp2 dig1 dig4 cp3 2 cp0 dig2 dig5 sw1 2 0 cp2 dig2 dig4 dig1 1 cp0 dig2 dig5 pwm0 2 cp1 dig3 dig0 sw2 3 0 cp0 dig3 dig5 dig2 1 cp1 dig3 dig0 pwm1 2 cp2 dig4 dig1 sw3 4 0 cp1 dig4 dig0 dig3 1 cp2 dig4 dig1 pwm5 2 cp0 dig5 dig2 sw4 5 0 cp2 dig5 dig1 dig4 1 cp0 dig5 dig2 cp3 2 cp1 dig0 dig3 sw5 product overview stlux385a 16/98 docid024387 rev 2 3.2.1 architecture and registers ? harvard architecture with 3-stage pipeline ? 32-bit wide program memory bus with single cycle fetching for most instructions ? x and y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter with 16 mbyte linear memory space ? 16-bit stack pointer with access to a 64 kbyte stack ? 8-bit condition code register with seven condition flags updated with the results of last executed instruction 3.2.2 addressing ? 20 addressing modes ? indexed indirect addressing mode for lookup tables located in the entire address space ? stack pointer relative addressing mode for efficient implementation of local variables and parameter passing 3.2.3 instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumulator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers 3.2.4 single wire interface module (swim) the single wire interface module (swim), together with the integrated debug module (dm), permits non-intrusive, real-time in-circuit debugging and fast memory programming. the interface can be activated in all device operation modes and can be connected to a running device (hot plugging).the maximum data transmission speed is 145 byte/ms. 3.2.5 debug module the non-intrusive debugging module features a performance close to a full-featured emulator. besides memory and peripheral operation, cpu operation can also be monitored in real-time by means of shadow registers. ? r/w of ram and peripheral registers in real-time ? r/w for all resources when the application is stopped ? breakpoints on all program-memory instructions (software breakpoints), except for the interrupt vector table ? two advanced breakpoints and 23 predefined breakpoint configurations docid024387 rev 2 17/98 stlux385a product overview 3.3 basic peripherals the following sections describe the basic peripherals accessed by the internal cpu controller. 3.3.1 vectored interrupt controller ? nested interrupts with three software priority levels ? 21 interrupt vectors with hardware priority ? two vectors for 12 external maskable or un-maskable interrupt request lines ? trap and reset interrupts 3.3.2 timers the stlux385a device provides several timers which are used by software and do not interact directly with the smed and the pwm generation. system timers the system timer consists of a 16-bit auto-reload counter driven by a programmable prescaled clock and operating in one shoot or free running operating mode. the timer is used to provide the ic time base system clock, with interrupt generation on timer overflow events. auxiliary timer the auxiliary timer is a light timer with elementary functionality. the time base frequency is provided by the cco clock logic (configurable with different source clock and prescale division factors), while the interrupt functionality is supplied by an interrupt edge detection logic similarly to the solution adopted for port p0/p2. the timer has the following main features: ? free running mode ? up counter ? timer prescaler 8-bit ? interrupt timer capability: ? vectored interrupt ? interrupt irq/nmi or polling mode ? timer pulse configurable as a clock output signal via cco primary pin thanks to the great configurability of the cco frequency, the timer can cover a wide range of interval time to fit better the target application requirements. auto-wakeup timer the awu timer is used to cyclically wake up the ic device from the active-halt state. the awu frequency time base f awu can be selected between the following clock sources: lsi (153.6 khz) and the external clock hse scaled down to 128 khz clock. product overview stlux385a 18/98 docid024387 rev 2 by default the f awu clock is provided by the lsi internal source clock. watchdog timers the watchdog system is based on two independent timers providing a high level of robustness to the applications. the watchdog timer activity is controlled by the application program or by suitable option bytes. once the watchdog is activated, it cannot be disabled by the user program without going through reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which causes the application program to break the normal operating sequence. the window function can be used to adjust the watchdog intervention period in order to match the application timing perfectly. the application software must refresh the counter before time-out and during a limited time window. if the counter is refreshed outside this time window, a reset is issued. independent watchdog timer the independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures. it is clocked by the 153.6 khz lsi internal rc clock source. if the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. 3.4 flash program and data e 2 prom embedded flash and e 2 prom with memory ecc code correction and protection mechanism preventing embedded program hacking. ? 32 kbyte of single voltage program flash memory ? 1 kbyte true (not emulated) data e 2 prom ? read while write: writing in the data memory is possible while executing code program memory ? the device setup is stored in a user option area in the non-volatile memory docid024387 rev 2 19/98 stlux385a product overview 3.4.1 architecture figure 5. flash and e 2 prom internal memory organizations ? the memory is organized in blocks of 128 bytes each ? read granularity: 1 word = 4 bytes ? write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel ? writing, erasing, word and block management is handled automatically by the memory interface 3.4.2 write protection (wp) write protection in application mode is intended to avoid unintentional overwriting of the memory. the write protection can be removed temporarily by executing a specific sequence in the user software. 3.4.3 protection of user boot code (ubc) in the stlux385a a memory area of 32 kbyte can be protected from overwriting at user option level. in addition to the standard write protection, the ubc protection can exclusively be modified via the debug interface, the user software cannot modify the ubc protection status. the ubc memory area contains the reset and interrupt vectors and its size can be adjusted in increments of 512 bytes by programming the ubc and nubc option bytes. note: if users choose to update the boot code in the application programming (iap), this has to be protected so to prevent unwanted modification. 3.4.4 read-out protection (rop) the stlux385a provides a read-out protection of the code and data memory which can be activated by an option byte setting. ubc area remains write protected during iap program memory area write access possible for iap data memory area (1kbytes) option bytes data eeprom memory flash program memory programmable area maximum 32 kbytes gipc080520131510fsr product overview stlux385a 20/98 docid024387 rev 2 the read-out protection prevents reading and writing program memory, data memory and option bytes via the debug module and swim interface. this protection is active in all device operation modes. any attempt to remove the protection by overwriting the rop option byte triggers a global erase of the program and data memory. the rop circuit may provide a temporary access for debugging or failure analysis. the temporary read access is protected by a user defined, 8-byte keyword stored in the option byte area. this keyword must be entered via the swim interface to temporarily unlock the device. if desired, the temporary unlock mechanism can be permanently disabled by the user. 3.5 clock controller the clock controller distributes the system clock provided by different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. the main clock controller features are: ? clock sources ? internal 16 mhz and 153.6 khz rc oscillators ? external source clock: ? crystal/resonator oscillator ? external clock input ? internal pll @ 96 mhz (not used as f master source clock) ? reset: after the reset the microcontroller restarts by default with an internal 2 mhz clock (16 mhz/8). the clock source and speed can be changed by the application program as soon as the code execution starts. ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. ? clock management: to reduce power consumption, the clock controller can stop the clock to the core or individual peripherals. ? wakeup: in case the device wakes up from low-power modes, the internal rc oscillator (16 mhz/8) is used for quick startup. after a stabilization time, the device switches to the clock source that was selected before halt mode was entered. ? clock security system (css): the css permits monitoring of external clock sources and automatic switching to the internal rc (16 mhz/8) in case of a clock failure. ? configurable main clock output (cco): this feature outputs the clock signal. 3.5.1 internal 16 mhz rc oscillator (hsi) the high speed internal (hsi) clock is the default master clock line, generated by an internal rc oscillator and with nominal frequency of 16 mhz. it has the following major features: ? rc architecture ? glitch free oscillation ? 3-bit user calibration circuit docid024387 rev 2 21/98 stlux385a product overview 3.5.2 internal 153.6 khz rc oscillator (lsi) the low speed internal (lsi) clock is a low speed clock line provided by an internal rc circuit. it drives both the independent watchdog (iwdg) circuit and the auto-wakeup unit (awu). it can also be used as a low power clock line for the master clock f master . 3.5.3 internal 96 mhz pll the pll provides a high frequency 96 mhz clock used to generate high frequency and accurate pwm waveforms. the input reference clock must be 16 mhz and may be sourced either by the internal hsi signal or by the external hse auxiliary input crystal oscillator line. the internal pll prescaled clock cannot be selected as f master . note: should the end application require a pwm signal with a high degree of stability over long periods, an external clock source connected to the hse auxiliary clock line as pll input reference clock, should be used. in this case, the external clock source determines the pwm output stability. 3.5.4 external clock input/crystal oscillator (hse) the high speed external clock (hse) allows the connection of an external clock generated, for example, by a highly accurate crystal oscillator. the hse is interconnected with the f master clock line and to several peripherals. it allows users to provide a custom clock characterized by a high level of precision and stability to meet the application requirements. hse supports two possible external clock sources with a maximum of 24 mhz: ? crystal/ceramic resonator interconnected with the hseoscin/hseoscout signals ? direct drive clock interconnected with the hseoscin signal the hseoscin and hseoscout signals are multifunction pins configurable through the i/o multiplex mechanism; for further information refer to section 5 . note: when hse is configured as f master source clock, the hse input frequency cannot be higher than 16 mhz. when the hse is the pll input reference clock, then the hse input frequency must be equal to 16 mhz. if hse is the reference for the smed or the adc logic, the input frequency can be configured up to 24 mhz. 3.6 power management for efficient power management, the application can be put in one of four different low- power modes. users can configure each mode to obtain the best compromise between the lowest power consumption, the fastest startup time and available wakeup sources. ? wait mode : in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active-halt mode with regulator on : in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto- wakeup unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active-halt mode with regulator off, but the wakeup time product overview stlux385a 22/98 docid024387 rev 2 is faster. the wakeup is triggered by the internal awu interrupt, external interrupt or reset. ? active-halt mode with regulator off : this mode is the same as active-halt with regulator on, except that the main voltage regulator is powered off, so the wakeup time is slower. ? halt mode : in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, while main voltage regulator is switched in power-off. wakeup is triggered by external event or reset. in all modes the cpu and peripherals remain permanently powered on, the system clock is applied only to selected modules. the ram content is preserved and the brown-out reset circuit remains enabled. 3.7 communication interfaces 3.7.1 digital addressable lighting interface (dali) dali (digital addressable lighting interface), standardized as iec 929, is the new interface for lighting control solutions defined by the lighting industry. the dali protocol is generally implemented in a dali communication module (dcm): a serial communication circuit designed for controllable electronic ballasts. ?ballast? is a device or circuit used to provide the required starting voltage and operating current for led, fluorescent, mercury or other electronic-discharge lamps. the stlux385a dali driver has the following characteristics. ? improved dali noise rejection filter (see section : dali noise rejection filter ) ? speed line:1.2, 2.4 and 4.8 khz transmission rate 10% ? forward payload: 16, 17, 18 and 24-bit message length ? backward payload: 8-bit message length. ? bi-directional communications ? monitor receiver line timeout 500 ms 10% ? polarity insensitive on dali_rx, dali_tx signal line ? interoperability with different message length ? configurable noise rejection filter on dali_rx input line ? maskable interrupt request line ? dali peripheral clock has slowed down to 153.6 khz in low speed operating mode dali noise rejection filter the stlux385a dali interface includes a noise rejection filter interconnected on the rx channel capable to remove any bounce, glitch or spurious pulse from the rx line. the filter can be configured via three registers: ? msc_dalicksel: selects the source clock of filter timing ? msc_dalickdiv: configures the clock prescaler value ? msc_daliconf: configures the filter count and operating mode docid024387 rev 2 23/98 stlux385a product overview 3.7.2 universal asynchronous receiver/transmitter (uart) uart is the asynchronous receiver/transmitter communication interface. ? sw flow control operating mode ? full duplex, asynchronous communications ? high precision baud rate generator system ? common programmable transmit and receive baud rates up to f master /16 ? programmable data word length (8 or 9-bit) ? configurable stop bit - support for 1 or 2 stop bit ? configurable parity control ? separate enable bits for transmitter and receiver ? interrupt sources: ? transmit events ? receive events ? error detection flags ? 2 interrupt vectors: ? transmitter interrupt ? receiver interrupt ? reduced power consumption mode ? wakeup from mute mode (by idle line detection or address mark detection) ? 2 receiver wakeup modes: ? address bit (msb) ? idle line product overview stlux385a 24/98 docid024387 rev 2 3.7.3 inter-integrated circuit interface (i 2 c) i 2 c (inter-integrated circuit) bus interface serves as an interface between the microcontroller and the serial i 2 c bus. it provides multi-master capability, and controls all i 2 c bus-specific sequencing, protocol, arbitration and timing. it supports standard and fast speed modes. ? parallel-bus/i 2 c protocol converter ? multi-master capability: the same interface can act as master or slave ? i 2 c master features: ? clock generation ? start and stop generation ? i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports different communication speeds: ? standard speed (up to 100 khz) ? fast speed (up to 400 khz) ? status flags: ? transmitter/receiver mode flag ? end-of-byte transmission flag ?i 2 c busy flag ? error flags: ? arbitration lost condition for master mode ? acknowledgment failure after address/ data transmission ? detection of misplaced start or stop condition ? overrun/underrun if clock stretching is disabled ? interrupt sources: ? communication interrupt ? error condition interrupt ? wakeup from halt interrupt ? wakeup capability: ? mcu wakes up from low power mode on address detection in slave mode 3.8 analog to digital converter (adc) the stlux385a includes a 10-bit successive approximation adc with 8 multiplexed input channels. the analog input signal can be amplified before conversion by a selectable gain docid024387 rev 2 25/98 stlux385a product overview of 1 or 4 times. the analog-to-digital converter can operate either in single or in continuous/circular modes. the adc unit has the following main features: ? 8 adc input channel ? 10-bit resolution ? single and continuous conversion mode ? independent channel gain value x1 or x4 to extend dynamic range and resolution to 12- bit equivalent ? interrupt events: ? eoc interrupt asserted on end of conversion cycle ? eos interrupt asserted on end of conversion sequences ? seq_full_en interrupt assert on sequencer buffer full ? adc input voltage range dependent on selected gain value ? selectable conversion data alignment ? individual registers for up to 8 successive conversions 3.9 analog comparators the stlux385a includes four independent fast analog comparator units (comp3-0). each comparator has an internal reference voltage. comp3 can be also configured to use an external reference voltage connected to cpm3 input pin. each comparator reference voltage is generated by a dedicated internal-only 4-bit dac unit. the main characteristics of the analog comparator unit (acu) are the following: ? each comparator has an internally configurable reference ? internal reference voltages configurable in 16 steps with 83 mv voltage grain from 0 v (gnd) to 1.24 v (voltage reference) ? two stage comparator architecture is used to reach a high gain ? comparator output stage value accessible from processor interface ? continuous fast cycle comparison time pinout and pin description stlux385a 26/98 docid024387 rev 2 4 pinout and pin description 4.1 pinout figure 6. tssop38 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 19 20 adcin[0] adcin[1] adcin[2] adcin[3] adcin[4] adcin[5] adcin[6] adcin[7] gpio1[0]/pwm[0] digin[0]/cco_clk digin1 gpio1[1]/pwm[1] gpio1[2]/pwm[2] digin[2] digin[3] gpio1[5]/pwm[5] swim nrst vdd vss vout gpio0[4]/dali_tx/i2c_sda/uart_tx gpio0[5]/dali_rx/i2c_scl/uart_rx gpio1[4]/pwm[4] digin[4]/i2c_sda digin[5]/i2c_scl gpio1[3]/pwm[3] vssa vdda cpp[0] cpp[1] cpm3 cpp[2] cpp[3] gpio0[1]/uart_rx/i2c_scl gpio0[0]/uart_tx/i2c_sda gpio0[3]/i2c_scl/hseoscin/uart_rx gpio0[2]/i2c_sda/hseoscout/uart_tx docid024387 rev 2 27/98 stlux385a pinout and pin description 4.2 pin description table 2. pin description pin number type pin name main function alternate function 1 alternate function 2 alternate function 3 1 i/o gpio1[0]/pwm[0] smed pwm channel 0 general purpose i/o 10 -- 2 i/o digin[0]/cco_clk digital input 0 configurable clock output signal (cco) -- 3 i digin[1] digital input 1 - - - 4 i/o gpio1[1]/pwm[1] smed pwm channel 1 general purpose i/o 11 -- 5 i/o gpio1[2]/pwm[2] smed pwm channel 2 general purpose i/o 12 -- 6 i digin[2] digital input 2 - - - 7 i digin[3] digital input 3 - - - 8 i/o gpio1[5]/pwm[5] smed pwm channel 5 general purpose i/o 15 -- 9 i/o swim swim data interface --- 10 i/o nrst reset - - - 11 ps vdd digital and i/o power supply --- 12 ps vss digital and i/o ground --- 13 ps vout 1.8 v regulator capacitor --- 14 i/o gpio0[4]/dali_tx general purpose i/o 04 dali data transmit -- 15 i/o gpio0[5]/dali_rx general purpose i/o 05 dali data receive -- 16 i/o gpio1[4]/pwm[4] smed pwm channel 4 general purpose i/o 14 -- 17 i digin[4] digital input 4 - - - 18 i digin[5] digital input 5 - - - 19 i/o gpio1[3]/pwm[3] smed pwm channel 3 general purpose i/o 13 -- 20 i/o gpio0[2]/i 2 c_sda/ hseoscout/uart_tx general purpose i/o 02 i 2 c data output crystal oscillator signal uart data transmit pinout and pin description stlux385a 28/98 docid024387 rev 2 4.3 input/output specifications the stlux385a device includes two different i/o types: ? normal i/os configurable either at 2 or 10 mhz (high sink) ? fast i/o operating at 12 mhz the stlux385a i/os are designed to withstand current injection. for a negative injection current of 4 ma, the resulting leakage current in the adjacent input does not exceed 1 a; further details are available in section 10 . 21 i/o gpio0[3]/i 2 c_scl/ hseoscin/uart_rx general purpose i/o 03 i 2 c clock input crystal oscillator signal / input frequency signal uart data receive 22 i/o gpio0[0]/uart_tx/i 2 c_scl general purpose i/o 00 uart data transmit -- 23 i/o gpio0[1]/uart_rx/i 2 c_scl general purpose i/o 01 uart data receive -- 24 i cpp[3] positive analog comparator input 3 --- 25 i cpp[2] positive analog comparator input 2 --- 26 i cpm3 negative analog comparator input 3 --- 27 i cpp[1] positive analog comparator input 1 --- 28 i cpp[0] positive analog comparator input 0 --- 29 ps vdda analog power supply --- 30 ps vssa analog ground - - - 31 i adcin[7] analog input 7 - - - 32 i adcin[6] analog input 6 - - - 33 i adcin[5] analog input 5 - - - 34 i adcin[4] analog input 4 - - - 35 i adcin[3] analog input 3 - - - 36 i adcin[2] analog input 2 - - - 37 i adcin[1] analog input 1 - - - 38 i adcin[0] analog input 0 - - - table 2. pin description (continued) pin number type pin name main function alternate function 1 alternate function 2 alternate function 3 docid024387 rev 2 29/98 stlux385a i/o multifunction signal configuration 5 i/o multifunction signal configuration several i/os have multiple functionalities selectable through the configuration mechanism described in the following sections. the stlux385a i/os are grouped into three different configurable ports: p0, p1 and p2. 5.1 multifunction configuration policy the stlux385a supports either a cold or warm multifunction signal configuration policy according to the content of the en_cold_cfg bit field, part of the gencfg option byte register. when en_cold_cfg bit is set, the cold configuration is selected and the multifunction signals are configured according to the values stored in the option bytes; otherwise when the en_cold_cfg bit is cleared (default case), the warm configuration mode is chosen and the multifunction pin functionality is configured through the miscellaneous registers. the configuration options and the proper configuration registers are detailed in the following table: the warm configuration is volatile, thus not maintained after a device reset. 5.2 port p0 i/o multifunction configuration signal port p0 multiplexes several input/output functionalities, increasing the device flexibility. the p0 port pins can be independently assigned to general purpose i/os or to internal peripherals. all communication peripherals and the external oscillator are hosted by port p0 pins. in order to avoid electrical conflicts on the user application board, the p0 signals are configured at reset as gpio0[5:0] inputs without pull-up resistors. once reset is released, the firmware application must initialize the inputs with the proper configuration according to the application needs. table 3. multifunction configuration registers en_cold_cfg configuration policy multifunction configuration registers 1 cold afr_iomxp0, afr_iomxp1 and afr_iomxp2 0 (default) warm misc_iomxp0, misc_iomxp1 and misc_iomxp2 i/o multifunction signal configuration stlux385a 30/98 docid024387 rev 2 5.2.1 alternate function p0 configuration signals the multifunction pins can be configured via one of the following two registers, depending on the overall configuration policy (warm/cold): ? cold configuration: afr_iomxp0 option byte registers (refer to section 8 ). after reset the p0 signals are configured in line with afr_iomxp0 contents. ? warm configuration: misc_iomxp0 miscellaneous register (refer to section 5.5 ). after reset, the p0 signals are configured as gpio input lines with pull-up disabled. the next table summarizes the port p0 configuration scheme. both registers msc_iomxp0 and afr_iomxp0 use the same register fields sel_p054, sel_p032 and sel_p010 which respectively control the bits [5,4], [3,2] and [1,0] of port p0. note: sel_p054, sel_p032, sel_p010 are register fields for both registers msc_iomxp0 and afr_iomxp0. the peripheral conflict (same resources selected on different pins at the same time) has to be prevented by sw configuration. when the i 2 c interface is selected either on gpio0[5:4] or on gpio0[3:2] signals the related i/o port speed has to be configured at 10 mhz by programming the gpio0 internal peripheral. 5.2.2 port p0 diagnostic signals the primary i/os can be used to trace the smed's state evolution. this feature allows the debug of the complex smed configurations. the trace selection can be enabled or disabled via register msc_iomxsmd. the diagnostic signal selection through msc_iomxsmd register overrides the functional configuration of msc_iomxp0 register. table 4. p0 internal multiplexing signals port p0 multifunction configuration signal port pins multifunction signal mux sel selection fields value (binary) p0[1,0] gpio0[1] gpio0[0] sel_p010 00 uart_rx uart_tx 01 i 2 c_scl i 2 c_sda 10 rfu reserved encoding 11 p0[3,2] gpio0[3] gpio0[2] sel_p032 00 i 2 c_scl i 2 c_sda 01 hseoscin hseoscout 10 uart_rx uart_tx 11 p0[5,4] gpio0[5] gpio0[4] sel_p054 00 dali_rx dali_tx 01 i 2 c_scl i 2 c_sda 10 uart_rx uart_tx 11 docid024387 rev 2 31/98 stlux385a i/o multifunction signal configuration the port p0[5:3] or p0[2:0] can be configured to output one or two different smeds? current state. 5.2.3 port p0 i/o functional multiplexing signal figure 7 shows an outline view of port p0 multi-function multiplexing scheme. figure 7. port p0 i/o functional multiplexing scheme note: where ?a/f(s) in? and ?a/f(s) out? signals are defined in section 4.2 . 5.2.4 p0 programmable pull-up and speed feature the i/o speed and pad pull-up resistance (47 k ) of port p0 may be configured through the gpio0 internal registers. 5.3 port p1 i/o multifunction configuration signal the port1 i/o multifunction pins, similarly to port0, can be individually configured through the following set of registers based on the selected device configuration policy: ? cold configuration: afr_iomxp1 option byte register (refer to section 8 ). after reset the p1 signals are configured in line with afr_iomxp1 contents. ? warm configuration: misc_iomxp1 miscellaneous register (refer to section 5.5 ). after reset the p1 signals are configured as pwm output lines. every port1 i/o can be configured to operate as a pwm output pin or a gpio. differently from port p0s, the pins are configured as pwm output signals by default after reset. the next table summarizes the port p1 configurations as selected by the register fields sel_p15?sel_p10 which respectively control the bits [5]?[0] of port p1. input output a/f(s) out p0_idr[5:0] p0_odr[5:0] a/f in - msc_iomxp0 - afr_iomxp0 a/f(s) in a/f out p0[5:0] gipc080520131629fsr i/o multifunction signal configuration stlux385a 32/98 docid024387 rev 2 note: sel_p15?sel_p10 are common register fields of both registers misc_iomxp1 and afr_iomxp1. the pwm default polarity level is configured by the register option byte gencfg. 5.3.1 port p1 i/o multiplexing signal the next figure shows an outline view of port p1 signal multiplex scheme. figure 8. port p1 i/o multiplexing scheme table 5. port p1 i/o multiplexing signal port p1 multifunction configuration signal output signal multi-function signal mux selection selection bits value (binary) p1[0] pwm[0] sel_p10 1 gpio1[0] 0 p1[1] pwm[1] sel_p11 1 gpio1[1] 0 p1[2] pwm[2] sel_p12 1 gpio1[2] 0 p1[3] pwm[3] sel_p13 1 gpio1[3] 0 p1[4] pwm[4] sel_p14 1 gpio1[4] 0 p1[5] pwm[5] sel_p15 1 gpio1[5] 0 input output pwm out p1_idr[5:0] p1_odr[5:0] - msc_iomxp1 - afr_iomxp1 pwm[5..0] p1[5:0] gipc080520131642fsr docid024387 rev 2 33/98 stlux385a i/o multifunction signal configuration note: the p1[5:0] output signals may be read back from the p1_idr register only when the pins are configured as gpio out or pwm signals. the pwm internal signal is read-back also by the its own smed through the smd i/o multifunction signal configuration stlux385a 34/98 docid024387 rev 2 5.4.1 p2 programmable pull-up feature the pad pull-up resistances (47 k ) of port2 signals are individually controllable by msc_inpp2aux1 register. 5.5 multifunction port configuration registers msc_iomxp0 (port p1 i/o mux control register) port0 i/o multifunction signal configurations register (for functionality description refers to section 5.2 ). bit 1-0: sel_p010[1:0] port0[1:0] i/o multiplexing scheme: 00: port0[1:0] are interconnected to gpio0[1:0] signals 01: port0[1:0] are interconnected to uart_rx and uart_tx signals 10: port0[1:0] are interconnected to i 2 c_scl and i 2 c_sda signals 11: rfu bit 3-2: sel_p032[1:0] port0[3:2] i/o multiplexing scheme: 00: port0[3:2] are interconnected to gpio0[3:2] signals 01: port0[3:2] are interconnected to i 2 c_scl and i 2 c_sda signals 10: port0[3:2] are interconnected to hseoscin and hseoscout analog signals 11: port0[3:2] are interconnected to uart_rx and uart_tx signals bit 5-4: sel_p054[1:0] port0[5:4] i/o multiplexing scheme: 00: port0[5:4] are interconnected to gpio0[5:4] signals 01: port0[5:4] are interconnected to dali_rx and dali_tx signals 10: port0[5:4] are interconnected to i 2 c_scl and i 2 c_sda signals 11: port0[5:4] are interconnected to uart_rx and uart_tx signals bit 7-6: rfu reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations offset: 0x2a default value: 0x00 76543210 rfu sel_p054[1:0] sel_p032[1:0] sel_p010[1:0] r r/w r/w r/w docid024387 rev 2 35/98 stlux385a i/o multifunction signal configuration msc_iomxp1 (port p1 i/o mux control register) port1 i/o multifunction signal configuration register (for functionality description refers to section 5.3 ). bit 0: sel_p10 port1[0] i/o multiplexing scheme: 0: port1[0] is interconnected to gpio1[0] signal 1: port1[0] is interconnected to pwm[0] signal bit 1: sel_p11 port1[1] i/o multiplexing scheme: 0: port1[1] is interconnected to gpio1[1] signal 1: port1[1] is interconnected to pwm[1] signal bit 2: sel_p12 port1[2] i/o multiplexing scheme: 0: port1[2] is interconnected to gpio1[2] signal 1: port1[2] is interconnected to pwm[2] signal bit 3: sel_p13 port1[3] i/o multiplexing scheme: 0: port1[3] is interconnected to gpio1[3] signal 1: port1[3] is interconnected to pwm[3] signal bit 4: sel_p14 port1[4] i/o multiplexing scheme: 0: port1[4] is interconnected to gpio1[4] signal 1: port1[4] is interconnected to pwm[4] signal bit 5: sel_p15 port1[5] i/o multiplexing scheme: 0: port1[5] is interconnected to gpio1[5] signal 1: port1[5] is interconnected to pwm[5] signal bit 7-6: rfu reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations offset: 0x2b default value: 0x3f 76543210 rfu sel_p15 sel_p14 sel_p13 sel_p12 sel_p11 sel_p10 rr/w i/o multifunction signal configuration stlux385a 36/98 docid024387 rev 2 msc_iomxp2 (port p2 i/o mux control register) port1 i/o multifunction signal configurations register (for functionality description refers to section 5.4 ). bit 3-0: rfu reserved; must be kept 0 during register writing for future compatibility bit 4: sel_p254 port2[5:4] i/o multiplexing scheme: 0: port2[5:4] are interconnected to i 2 c_scl and i 2 c_sda signals 1: port2[5:4] are interconnected to digin[5:4] signals bit 7-5: rfu reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations msc_inpp2aux1 (inpp aux register) bit 5-0: inpp2_pulctr[5:0] this register configures respectively the inpp2[5:0] pull-up functionality as follows: 0: enable pad pull-up features (enabled by default for compatibility with the stlux385) 1: disable pad pull-up bit 7-6: rfu reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations. note: msc_iomxp2 and msc_inpp2aux1 are addressable in indirect mode. offset: 0x13 (indirect area) default value: 0xff 76543210 rfu sel_p254 rfu r r/w r offset: 0x08 default value: 0x00 76543210 rfu inpp2_pulctr [5:0] rr/w docid024387 rev 2 37/98 stlux385a memory and register map 6 memory and register map 6.1 memory map overview this section describes the register map implemented by the stlux385a device. the following picture shows the main memory map organization. all registers and memory spaces are configured within the first 64 kbytes of memory, the remaining address spaces are kept reserved for future use. table 7. internal memory map address description 00.0000h 2 kb ram 00.07ffh stack 00.0800h 00.3fffh reserved 00.4000h 00.43ffh 1 kb data e 2 prom 00.4400h 00.47ffh reserved 00.4800h 00.487fh 128 option bytes 00.4880h 00.4fffh reserved 00.5000h 00.57ffh peripheral register region 00.5800h 00.5fffh reserved 00.6000h 00.67ffh 2 kb boot rom 00.6800h 00.7effh reserved 00.7f00h 00.7fffh core register region memory and register map stlux385a 38/98 docid024387 rev 2 by default the stack address is initialized at 0x07ff and rolls-over when it reaches the address value of 0x0400. 6.2 register map the following section shows the stlux385a memory map. 6.2.1 general purpose i/o gpio0 register map 6.2.2 general purpose i/o gpio1 register map 00.8000h 32 interrupt vectors 00.8080h 00.ffffh 32 kb program flash 01.0000h ff.ffffh reserved table 7. internal memory map (continued) address description table 8. general purpose i/o gpio0 register map address block register name register description 0x00.5000 gpio0 p0_odr output data 0x00.5001 p0_idr input data 0x00.5002 p0_ddr data direction 0x00.5003 p0_cr1 control register 1 0x00.5004 p0_cr2 control register 2 table 9. general purpose i/o gpio0 register map address block register name register description 0x00.5005 gpio1 p1_odr output data 0x00.5006 p1_idr input data 0x00.5007 p1_ddr data direction 0x00.5008 p1_cr1 control register 1 0x00.5009 p1_cr2 control register 2 docid024387 rev 2 39/98 stlux385a memory and register map 6.2.3 miscellaneous registers direct register address mode table 10. miscellaneous direct register address mode address block register name register description 0x00.5010 msc msc_cfgp00 p00 input line control 0x00.5011 msc_cfgp01 p01 input line control 0x00.5012 msc_cfgp02 p02 input line control 0x00.5013 msc_cfgp03 p03 input line control 0x00.5014 msc_cfgp04 p04 input line control 0x00.5015 msc_cfgp05 p05 input line control 0x00.5016 msc_cfgp20 p20 input line control 0x00.5017 msc_cfgp21 p21 input line control 0x00.5018 msc_cfgp22 p22 input line control 0x00.5019 msc_cfgp23 p23 input line control 0x00.501a msc_cfgp24 p24 input line control 0x00.501b msc_cfgp25 p25 input line control 0x00.501c msc_stsp0 port0 status 0x00.501d msc_stsp2 port2 status 0x00.501e msc_inpp2 port2 read 0x00.501f rfu reserved for future use 0x00.5020 msc_dacctr comparator4 and dac4 configuration 0x00.5021 msc_dacin0 dac0 input data 0x00.5022 msc_dacin1 dac1 input data 0x00.5023 msc_dacin2 dac2 input data 0x00.5024 msc_dacin3 dac3 input data 0x00.5025 msc_smdcfg01 smed 0-1 behavior 0x00.5026 msc_smdcfg23 smed 2-3 behavior 0x00.5027 msc_smdcfg45 smed 4-5 behavior 0x00.5028 msc_smswev smed software events 0x00.5029 msc_smunlock smed unlock 0x00.502a msc_cboxs0 connection matrix selection for smed 0 memory and register map stlux385a 40/98 docid024387 rev 2 indirect register address mode 6.2.4 flash and e 2 prom non-volatile memories table 11. miscellaneous indirect register address mode address (idx) block register name register description 0x00 ? 0x04 msc rfu reserved for future use 0x05 msc_dalicksel dali clock selection 0x06 msc_dalickdiv dali filter clock division factor 0x07 msc_daliconf dali filter mode configuration 0x08 msc_inpp2aux1 inpp2 auxiliary configuration register 1 0x09 msc_inpp2aux2 inpp2 auxiliary configuration register 2 0x0a ? 0x12 rfu reserved for future use 0x13 msc_iomxp2 port2 alternate function mux register table 12. non-volatile memory register map address block register name register description 0x00.505a mif flash_cr1 control register 1 0x00.505b flash_cr2 control register 2 0x00.505c flash_ncr2 control register 2 (protection) 0x00.505d flash_fpr memory protection 0x00.505e flash_nfpr memory protection (complemented reg.) 0x00.505f flash_iapsr flash status 0x00.5062 flash_pukr write memory protection removal key reg. 0x00.5063 rfu reserved for future use 0x00.5064 flash_dukr write memory protection removal data 0x00.5071 flash_wait time access wait-state reg. docid024387 rev 2 41/98 stlux385a memory and register map 6.2.5 reset register table 13. rst_sr register map address block register name register description 0x00.50b3 rstc rst_sr reset control status memory and register map stlux385a 42/98 docid024387 rev 2 6.2.6 clock and clock controller table 14. clock and clock controller register map address block register name register description 0x00.50b4 ckc clk_smd0 smed 0 clock configuration 0x00.50b5 clk_smd1 smed 1 clock configuration 0x00.50b6 clk_smd2 smed 2 clock configuration 0x00.50b7 clk_smd3 smed 3 clock configuration 0x00.50b8 clk_smd4 smed 4 clock configuration 0x00.50b9 clk_smd5 smed 5 clock configuration 0x00.50ba rfu reserved for future use 0x00.50bb rfu reserved for future use 0x00.50bc rfu reserved for future use 0x00.50bd rfu reserved for future use 0x00.50be clk_plldiv pll clock divisor 0x00.50bf clk_awudiv awu clock divisor 0x00.50c0 clk_ickr internal clock control 0x00.50c1 clk_eckr external clock control 0x00.50c2 clk_pllr pll control 0x00.50c3 clk_cmsr clock master 0x00.50c4 clk_swr clock switch 0x00.50c5 clk_swcr switch control 0x00.50c6 clk_ckdivr clock dividers 0x00.50c7 clk_pckenr1 peripherals clock 0x00.50c8 clk_cssr clock security system 0x00.50c9 clk_ccor configurable clock output 0x00.50ca clk_pckenr2 peripheral clock enable 0x00.50cb rfu reserved for future use 0x00.50cc clk_hsitrimr hsi calibration trimmer 0x00.50cd clk_swimccr swim clock division 0x00.50ce clk_ccodivr cco divider 0x00.50cf clk_adcr adc clock configuration docid024387 rev 2 43/98 stlux385a memory and register map 6.2.7 wwdg timers 6.2.8 iwdg timers 6.2.9 awu timers table 15. wwdg timer register map address block register name register description 0x00.50d1 wwdg wwdg_cr watchdog control 0x00.50d2 wwdg_wr watchdog window table 16. iwdg timer register map address block register name register description 0x00.50e0 iwdg iwdg_kr watchdog key 0x00.50e1 iwdg_pr watchdog time base 0x00.50e2 iwdg_rlr watchdog counter value after reload table 17. awu timer register map address block register name register description 0x00.50f0 awu awu_csr awu control status 0x00.50f1 awu_apr awu asynchronous prescaler buffer 0x00.50f2 awu_tbr awu time base selection memory and register map stlux385a 44/98 docid024387 rev 2 6.2.10 inter-integrated circuit interface (i 2 c) table 18. i 2 c register map address block register name register description 0x00.5210 i2c i 2 c_cr1 i 2 c control register 1 0x00.5211 i 2 c_cr2 i 2 c control register 2 0x00.5212 i 2 c_freqr i 2 c frequency register 0x00.5213 i 2 c_oarl i 2 c own add-low reg. 0x00.5214 i 2 c_oarh i 2 c own add-high reg. 0x00.5215 rfu reserved for future use 0x00.5216 i 2 c_dr i 2 c data register 0x00.5217 i 2 c_sr1 i 2 c status register 1 0x00.5218 i 2 c_sr2 i 2 c status register 2 0x00.5219 i 2 c_sr3 i 2 c status register 3 0x00.521a i 2 c_itr i 2 c interrupt and dma control 0x00.521b i 2 c_ccrl i 2 c clock control 0x00.521c i 2 c_ccrh i 2 c clock control 0x00.521d i 2 c_triser i 2 c rising edge docid024387 rev 2 45/98 stlux385a memory and register map 6.2.11 universal asynchronous receiver/transmitter (uart) 6.2.12 system timer registers table 19. uart register map address block register name register description 0x00.5230 uart uart_sr uart status 0x00.5231 uart_dr uart data 0x00.5232 uart_brr1 uart baud rate div mantissa [7:0] 0x00.5233 uart_brr2 uart baud rate div mantissa [11:8] scidiv fract[3:0] 0x00.5234 uart_cr1 uart control register 1 0x00.5235 uart_cr2 uart control register 2 0x00.5236 uart_cr3 uart control register 3 0x00.5237 uart_cr4 uart control register 4 0x00.5238 uart_cr5 uart control register 5 0x00.5239 uart_gtr uart guard time 0x00.523a uart_pscr sci1 prescaler table 20. system timer register map address block register name register description 0x00.5340 stmr stmr_cr1 control register 1 0x00.5341 stmr_ier interrupt enable 0x00.5342 stmr_sr1 status register 1 0x00.5343 stmr_egr event generation 0x00.5344 stmr_cnth counter high 0x00.5345 stmr_cntl counter low 0x00.5346 stmr_pscl prescaler low 0x00.5347 stmr_arrh auto-reload high 0x00.5348 stmr_arrl auto-reload low memory and register map stlux385a 46/98 docid024387 rev 2 6.2.13 digital addressable lighting interface (dali) 6.2.14 analog-to-digital converter (adc) the adc_datl/h register number docid024387 rev 2 47/98 stlux385a memory and register map 6.2.15 state machine event driven (smeds) the smed memory and register map stlux385a 48/98 docid024387 rev 2 table 23. smed register map address (offset) block register name register description 0x00 smed docid024387 rev 2 49/98 stlux385a memory and register map 6.2.16 cpu register note: register space accessible in debug mode only. 0x1b smed memory and register map stlux385a 50/98 docid024387 rev 2 6.2.17 global configuration register 6.2.18 interrupt controller 6.2.19 swim control register table 25. cfg_gcr register map address block register name register description 0x00.7f60 gcr cfg_gcr global configuration table 26. interrupt software priority register map address block register name register description 0x00.7f70 itc itc_spr0 interrupt sw priority register 0 0x00.7f71 itc_spr1 interrupt sw priority register 1 0x00.7f72 itc_spr2 interrupt sw priority register 2 0x00.7f73 itc_spr3 interrupt sw priority register 3 0x00.7f74 itc_spr4 interrupt sw priority register 4 0x00.7f75 itc_spr5 interrupt sw priority register 5 0x00.7f76 itc_spr6 interrupt sw priority register 6 0x00.7f77 itc_spr7 interrupt sw priority register 7 table 27. swim register map address block register name register description 0x00.7f80 swim swim_csr swim control status docid024387 rev 2 51/98 stlux385a interrupt table 7 interrupt table the following table shows the stlux385a internal controller's interrupt. table 28. interrupt vector exception table priority source block description wakeup from halt wakeup from active-halt interrupt vector address reset reset yes yes 8000h trap software interrupt 8004h 0 nmi nmi (not maskable interrupt) yes (1) yes (1) 8008h 1 awu auto-wakeup from halt yes 800ch 2 ckc clock controller 8010h 3 po gpio0[5:0]external interrupts yes yes 8014h 4 auxtim auxiliary timer 8018h 5 p2 digin[5:0] external interrupts yes yes 801ch 6 smed0 smed-0 control logic 8020h 7 smed1 smed-1 control logic 8024h 8 rfu reserved for future use 8028h 9 rfu reserved for future use 802ch 10 rfu reserved for future use 8030h 11 rfu reserved for future use 8034h 12 rfu reserved for future use 8038h 13 rfu reserved for future use 803ch 14 rfu reserved for future use 8040h 15 smed2 smed-2 control logic 8044h 16 smed3 smed-3 control logic 8048h 17 uart tx complete 804ch 18 uart receive register data full indirect (2) indirect (2) 8050h 19 i 2 ci 2 c interrupt indirect (2) yes 8054h 20 rfu reserved for future use 8058h 21 rfu reserved for future use 805ch 22 adc end of conversion 8060h 23 sys-tmr update/overflow 8064h 24 flash eop/wr_pg_dis 8068h 25 dali dali interrupt line indirect (1) indirect (1) 806ch 26 smed4 smed-4 control logic 8070h 27 smed5 smed-5 control logic 8074h interrupt table stlux385a 52/98 docid024387 rev 2 28 rfu reserved future use 8078h 29 rfu reserved future use 807ch 1. p0[x] may be configured to generate an nmi request. 2. p0[x] may be configured to generate an irq request. table 28. interrupt vector exception table (continued) priority source block description wakeup from halt wakeup from active-halt interrupt vector address docid024387 rev 2 53/98 stlux385a option bytes 8 option bytes the user option byte is a memory e2prom area allowing users to customize the ic device major functionalities: ? rop: read-out protection control field ? ubc: user boot code protection ? pwm: configurable reset output value ? wdg: internal watchdog hw configuration ? afr: alternate multifunction signals configuration ? ckc: clock controller functionalities (pll, hse enable, awu clock selection?) ? hse: clock stabilization counter ? wait: flash and e2prom wait state access time has to be configured with value 0x00 ? boot: configurable internal boot sources ? bl: boot-loader control sequences except the rop byte all the other option bytes are stored twice in a regular (opt) and complemented format (nopt) for redundancy. the option byte can be programmed in icp mode through the swim interface or in iap mode by the application with the exception of the rop byte that can be only configured via swim interface. refer to the stm8 flash programming manual (pm0047) for further information about flash programming. refer to stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. option bytes stlux385a 54/98 docid024387 rev 2 8.1 option byte register overview table 29. option byte register overview address option name option bits default settings 76543210 4800h rop rop[7:0] 00h 4801h ucb ubc[7:0] 00h 4802h nucb nubc[7:0] ffh 4803h gencfg rst_pwm5 rst_pwm4 rst_ pwm3 rst_pwm2 rst_pwm1 rst_pwm0 comp1_2 en_cold_c fg 00h 4804h ngencfg nrst_pwm5 nrst_pwm4 nrst_pwm3 nrst_pwm2 nrst_pwm1 nrst_pwm0 ncomp1_2 nen_cold_ cfg ffh 4805h miscuopt - - - - lsi_en iwdg_hw wwdg_hw wwdg_hal t 28h 4806h nmiscuopt - - - - nlsi_en niwdg_hw nwwdg_h w nwwdg_ha lt d7h 4807h clkctl - - - cckawuse l1 extclk cckawuse l0 prsc[1:0] 09h 4808h nclkctl - - - ncckawus el1 nextclk ncckawus el0 np rsc[1:0] f6h 4809h hsestab hsecnt[7:0] 00h 480ah nhsestab nhsecnt[7:0] ffh 480bh - 480ch reserved - 00h - ffh 480dhwaitstate------ ws[1:0]00h 480eh nwaitstate - - - - - - nws[1:0] ffh 480fh afr_iomxp 0 - - sel_p054[1:0] sel_p032[1:0] sel_p010[1:0] 00h stlux385a option bytes docid024387 rev 2 55/98 note: the default setting values refer to the factory configuration.the factory configuration can be overwritten by the user in accordance with the target application requirements. this area of memory may be erased by the global flash erase instruction generated by an unauthorized attempt to modify the rop protection. 4810h nafr_iomx p0 - - nsel_p054[1:0] nsel_p032[1:0] nsel_p010[1:0] ffh 4811h afr_iomxp 1 auxtim - sel_p15 sel_p14 sel_p13 sel_p12 sel_p11 sel_p10 00h 4812h nafr_iomx p1 nauxtim - nsel_p15 nsel_p14 nsel_p13 nsel_p12 nsel_p11 nsel_p10 ffh 4813h afr_iomxp 2 ---sel_p254----00h 4814h nafr_iomx p2 ---nsel_p254----ffh 4815h msc_opt0 - - uartline(1:0) - botsel[2:0] 00h 4816h nmsc_opt0 - - nuartline(1:0) - nbotsel[2:0] ffh 487dhreserved--------00h 487eh optbl bl(7:0) 00h 487fh noptbl nbl(7:0) ffh table 29. option byte register overview (continued) address option name option bits default settings 76543210 option bytes stlux385a 56/98 docid024387 rev 2 8.2 option byte register description the option byte registers are mapped inside the e2prom data region. rop (memory read-out protection register) bit 7-0: rop[7:0] memory read-out protection: 0xaa: enable read-out protection. when read-out protection is enabled, reading or modifying the flash program memory and data area in icp mode (using the swim interface) is forbidden, whatever the write protection settings are. ubc (ubc user boot code reg.) bit 7-0: ubc[7:0] user boot code write protection memory size: 0x00: no ubc, no flash memory write-protection 0x01: pages 0 to 1 defined as ubc; 1 kbyte memory write-protected (0x00.8000- 0x00.83ff) 0x02: pages 0 to 3 defined as ubc; 2 kbyte memory write-protected (0x00.8000- 0x00.87ff) 0x03: pages 0 to 4 defined as ubc; 2.5 kbyte memory write-protected (0x00.8000- 0x00.89ff) ... 0x3e: pages 0 to 63 defined as ubc; 32 kbyte memory write-protected (0x00.8000- 0x00.ffff) other values: reserved offset: 0x004800 default value: 0x00 76543210 rop [7:0] r/w offset: 0x004801 default value: 0x00 76543210 ubc [7:0] r/w docid024387 rev 2 57/98 stlux385a option bytes nubc (ubc user boot code reg. protection) nubc: not(ubc) emc byte protection. gencfg (general configuration reg.) bit 0: en_cold_cfg enables ic cold configuration through the option byte register afr_iomxp0,p1: 0: default case, the ic multifunction signal configuration is performed by the miscellaneous registers msc_iomxp0 and msc_iomxp1 (warm configuration). 1: enables the multifunction signal configuration through the option byte registers afr_iomxp0 and afr_iomxp1 (cold configuration). bit 1: comp1_2 enables the complete backward compatibility with the previous device implementations. in detail, below features are inhibited: multiplexing of i 2 c interface on gpio[5:4], gpio[1:0], digin[5:4] multiplexing of uart interface on gpio[5:4] port0 and port2 interrupt mask feature (polling) digin[5:0] pull-up disabling feature dali noise rejection filter note: this bit setting ensures the full device compatibility with the previous device model (stlux385). offset: 0x004802 default value: 0xff 76543210 nubc [7:0] r/w offset: 0x004803 default value: 0xff 765432 1 0 rst_pwm [5:0] comp1_2 en_cold_c fg r/w r/w r/w option bytes stlux385a 58/98 docid024387 rev 2 bit 7:2: rst_pwm[5:0] configures the pwm[n] reset value after the nrst signal 0: pwm[n] output low level (native default value) 1: pwm[n] output high level note: the pwm signal programmed reset value is configured during the option byte loader phase, then before the nrst is released it assumes its proper initial values. ngencfg (general configuration reg. protect.) ngencfg: not(gencfg) emc byte protection miscuopt (miscellaneous config. reg.) bit 0: wwdg_halt window watchdog reset on halt: 0: no reset generated on halt if wwdg is active 1: reset generated on halt if wwdg is active bit 1: wwdg_hw window watchdog hardware enable: 0: window watchdog activation by sw 1: window watchdog activation by hw bit 2: iwdg_hw independent watchdog hardware enable: 0: independent watchdog activation by sw 1: independent watchdog activation by hw offset: 0x004804 default value: 0xff 765432 1 0 rst_pwm [5:0] ncomp1_2 nen_cold_c fg r/w r/w r/w offset: 0x004805 default value: 0x28 (factory configuration) 7654321 0 rfu rfu rfu lsi_en lwdg_hw wwdg_hw wwdg_hal t r r r r/w r/w r/w r/w docid024387 rev 2 59/98 stlux385a option bytes bit 3: lsi_en low speed internal rcosc clock enable: 0: lsi clock is not available to cpu 1: lsi cock is enabled for cpu bit 4: rfu reserved; must be kept 0 during register writing for future compatibility bit 5: rfu reserved; must be kept 1 during register writing for future compatibility bit 7-6: rfu reserved; must be kept 0 during register writing for future compatibility nmiscuopt (miscellaneous config. reg. protect.) nmiscuopt: not(miscuopt) emc byte protection clkctl (ckc configuration reg.) bit 1-0: prsc[1:0] prescaler value for hse to provide awu unit with the low speed clock: 00: 24 mhz to 128 khz prescaler 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler offset: 0x004806 default value: 0xd7 76 5 4 3 2 1 0 rfu rfu rfu nlsi_en nlwdg_hw nwwdg_hw nwwdg_hal t r r r r/w r/w r/w r/w offset: 0x004807 default value: 0x09 (factory configuration) 765 4 3 2 1 0 rfu ckawusel1 extclk ckawusel0 prsc [1:0] r r/w r/w r/w r/w option bytes stlux385a 60/98 docid024387 rev 2 bit 3: extclk external clock selection: 0: external crystal oscillator clock connected to hseoscin and hseoscout signals 1: external direct drive clock connected to hseoscin bit 4,2: ckawusel[1:0] awu clock selection: 00: low speed internal clock used for awu module 01: hse high speed external clock with prescaler used for awu module 10: reserved encoding value 11: reserved encoding value bit 7-5: rfu reserved; must be kept 0 during register writing for future compatibility nclkctl (ckc configuration reg.) nclkctl: not(clkctl) emc byte protection. hsestab (hse clock stabilization reg.) bit 7-0: hsecnt[7:0] hse crystal oscillator stabilization cycles: 0x00: 2048 clock cycles 0xb4: 128 clock cycles 0xd2: 8 clock cycles 0xe1: 0.5 clock cycles offset: 0x004808 default value: 0xf6 (factory configuration) 765 4 3 2 1 0 rfu nckawusel1 nextclk nckawusel0 nprsc [1:0] r r/w r/w r/w r/w offset: 0x004809 default value: 0x00 765432 1 0 hsecnt [7:0] r/w docid024387 rev 2 61/98 stlux385a option bytes nhsestab (hse clock stabilization reg. protect.) nhsestab: not(hsestab) emc byte protection. waitstate (flash wait state reg.) bit 1-0: waitstat[1:0] configures the e2prom and flash programmable delay read access time: 00: 0 no delay cycle (default case f master @16 mhz) 01: 1 delay cycles 10: 2 delay cycles 11: 3 delay cycles bit 7-2: rfu reserved; must be kept 0 during register writing for future compatibility nwaitstate (flash wait state reg.) nwaitstate: not(waitstate) emc byte protection. offset: 0x00480a default value: 0xff 765432 1 0 nhsecnt [7:0] r/w offset: 0x00480d default value: 0x00 765432 1 0 rfu waitstat [1:0] rr/w offset: 0x00480e default value: 0xff 765432 1 0 rfu nwaitstat [1:0] rr/w option bytes stlux385a 62/98 docid024387 rev 2 afr_iomxp0 (alternative port0 config. reg.) bit 5-0: refer to msc_iomxp0 miscellaneous register field description section 6.2 bit 7-6: rfu reserved; must be kept 0 during register writing for future compatibility nafr_iomxp0 (alternative port0 config. reg. protect.) nafr_iomxp0: not(afr_iomxp0) emc byte protection. afr_iomxp1 (alternative port1 config. reg.) bit 5-0: refer to msc_iomxp1 miscellaneous register field description section 6.2.3 bit 6: rfu reserved; must be kept 0 during register writing for future product compatibility offset: 0x00480f default value: 0x00 765432 1 0 rfu sel_p054 [1:0] sel_p032 [1:0] sel_p010 [1:0] r r/w r/w r/w offset: 0x004810 default value: 0xff 765432 1 0 rfu nsel_p054 [1:0] nsel_p032 [1:0] nsel_p010 [1:0] r r/w r/w r/w offset: 0x004811 default value: 0x00 765432 1 0 auxtim rfu sel_p15 sel_p14 sel_p13 sel_p12 sel_p11 sel_p10 r r r/w r/w r/w r/w r/w r/w docid024387 rev 2 63/98 stlux385a option bytes bit 7: auxtim cco aux timer compatibility features 0: cco aux timer enabled 1: cco aux timer disabled nafr_iomxp1 (alternative port1 config. reg. protect) nafr_iomxp1: not(afr_iomxp1) emc byte protection. afr_iomxp2 (alternative port2 config. reg.) bit 3-0: rfu reserved; must be kept 0 during register writing for future product compatibility bit 4: refer to msc_iomxp2 miscellaneous register field description section 6.2.3 bit 7-5: rfu reserved; must be kept 0 during register writing for future product compatibility nafr_iomxp2: not(afr_iomxp2) emc byte protection. offset: 0x004812 default value: 0xff 765432 1 0 nauxtim rfu nsel_p15 nsel_p14 nsel_p13 nsel_p12 nsel_p11 nsel_p10 r r r/w r/w r/w r/w r/w r/w offset: 0x004811 default value: 0x00 765432 1 0 rfu sel_p254 rfu rfu rfu rfu rrrrrr offset: 0x004812 default value: 0xff 765432 1 0 rfu nsel_p254 rfu rfu rfu rfu rrrrrr option bytes stlux385a 64/98 docid024387 rev 2 msc_opt0 (misc. config. reg0.) bit 2-0: bootsel[2:0] boot-rom peripheral enables: 000: automatic scan boot sources; this selection enables the automatic scan configuration sequence of all possible initializing peripheral devices: periph0(uart), periph1(rfu), periph2(rfu). 001: enable boot source: periph0 010: enable boot source: periph1 011: enable boot sources: periph1, periph0 100: enable boot source: periph2 101: enable boot sources: periph2, periph0 110: enable boot sources: periph2, periph1 111: enable boot sources: periph2, periph1, periph0 bit 3: rfu reserved; must be kept 0 during register writing for future compatibility bit 5-4: uartline[1:0] selects the uart port configuration pins involved during the bootload sequence in warm configuration mode; in case of cold configuration, this field is ignored since the uart port is selected by register afr_ioxp0. 00: boot sequence with uart i/f configured in all possible uart multiplexed signal schemes. this sequence is used when uart i/f position is not specified. 01: boot sequence with uart i/f configured on p0(1,0) 10: boot sequence with uart i/f configured on p0(3,2) 11: boot sequence with uart i/f configured on p0(5,4) bit 7-6: rfu reserved; must be kept 0 during register writing for future compatibility offset: 0x004815 default value: 0x00 765432 1 0 rfu uartline [1:0] rfu bootsel [2:0] r r/w r r/w docid024387 rev 2 65/98 stlux385a option bytes nmsc_opt0 (misc. config. reg0. protect) nmsc_opt0: not(msc_opt0) emc byte protection. optbl (option byte bootloader) bit 7-0: bl[7:0] bootloader field checked by the internal bootrom code during the stlux385a initialization phase. the content of register locations 0x00487e, 0x00487f and 0x008000 determine the bootloader sw flow execution sequence. optbl (option byte boot loader protect.) noptbl: not(optbl) emc byte protection. offset: 0x004816 default value: 0xff 765432 1 0 rfu uartline [1:0] rfu nbootsel [2:0] r r/w r r/w offset: 0x00487e default value: 0x00 765432 1 0 bl [7:0] r/w offset: 0x00487f default value: 0x00 765432 1 0 nbl [7:0] r/w device identification stlux385a 66/98 docid024387 rev 2 9 device identification 9.1 unique id the stlux385a provides a 56-bits unique identifier code usable as device identification number which can be used to increase the device security. the unique id code is a frozen signature not alterable by user. the unique device identifier is ideally used by the application software and is suited for: ? serial code ? security keys in conjunction with cryptographic software to increase the embedded flash code security ? activating the secure boot sequence 9.2 device id the stlux385a device identification model is coded in the following register area and it cannot be altered by the user. the register fields have the follow meaning: dev_id [7:0]: device identification model 0x00: stlux385 others: rfu reserved values rev_id [4:0]: revision identification model 00000: stlux385 00001: stlux385a others: rfu reserved values table 30. unique id register overview address option name unique id bits 7654321 0 48e0h uid0 lotnum[7:0] 48e1h uid1 lotnum[15:8] 48e2h uid2 lotnum[23:16] 48e3h uid3 wafernum[4:0] xcoord[7:5] 48e4h uid4 xcoord[4:0] ycoord[7:5] 48e5h uid5 ycoord[4:0] lotnum[42:40] 48e6h uid6 lotnum[31:24] 48e7h uid7 lotnum[39:32] docid024387 rev 2 67/98 stlux385a device identification table 31. dev id register overview address option name dev id bits default settings 76543210 4896h dvd0 dev_id[7:0] 00h 4897h ndvd0 ndev_id[7:0] ffh 4898h dvd1 rfu rev_id[4:0] 01h 4899h ndvd1 nrfu nrev_id[4:0] feh electrical characteristics stlux385a 68/98 docid024387 rev 2 10 electrical characteristics 10.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . v dda and v dd must be connected to the same voltage value. 10.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max. (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 10.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd and v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range. 10.1.3 typical curves unless otherwise specified, all typical curves are given as design guidelines only and are not tested. 10.1.4 typical current consumption for typical current consumption measurements, v dd and v dda are connected together as shown in the following picture. figure 9. supply current measurement conditions gipd090520131534fsr 5 v or 3.3 v vddio vddia gndio gnda docid024387 rev 2 69/98 stlux385a electrical characteristics 10.1.5 loading capacitors the loading conditions used for pin parameter measurement are shown in the following picture: figure 10. pin loading conditions 10.1.6 pin output voltage the input voltage measurement on a pin is described in the following picture. figure 11. pin input voltage gipd090520131536fsr 50 pf gipd090520131542fsr v in electrical characteristics stlux385a 70/98 docid024387 rev 2 10.2 absolute maximum ratings stresses above those listed as 'absolute maximum ratings' may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect the device reliability. table 32. voltage characteristics symbol ratings min. max. unit v ddx ? v ssx supply voltage (1) 1. all power v ddx (v dd , v dda ) and ground v ssx (v ss , v ssa ) pins must always be connected to the external power supply. -0.3 6.5 v v in input voltage on any other pin (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . v ss -0.3 v dd +0.3 v dd - v dda variation between different power pins 50 mv v ss - v ssa variation between all the different ground pins (3) 3. v ss and v ssa signals must be interconnected together with a short wire loop. 50 v esd electrostatic discharge voltage refer to absolute maximum ratings (electrical sensitivity) on section 10.4.1 table 33. current characteristics symbol ratings max. (1) 1. data based on characterization results, not tested in production. unit i vddx total current into v ddx power lines (2) 2. all power v ddx (v dd , v dda ) and ground v ssx (v ss , v ssa ) pins must always be connected to the external power supply. 100 ma i vssx total current out of v ssx power lines (2) 100 i io output current sunk by any i/os and control pin ref. output current source by any i/os and control pin i inj(pin) (3) (4) 3. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . 4. negative injection disturbs the analog performance of the device. injected current on any pin 4 i inj(tot) (3)(4)(5) 5. when several inputs are submitted to a current injection, the maximum iinj(pin) is the absolute sum of the positive and negative injected currents (instantaneous va lues). these results are based on characterization with iinj(pin) maximum current injection on four i/o port pins of the device. sum of injected currents 20 docid024387 rev 2 71/98 stlux385a electrical characteristics 10.3 operating conditions the device must be used in operating conditions that respect the parameters in the table below. in addition, full account must be taken for all physical capacitor characteristics and tolerances. table 34. thermal characteristics symbol ratings max. unit t stg storage temperature range -65 to 150 oc t j maximum junction temperature 150 table 35. general operating conditions symbol parameter conditions min. typ. max. unit f cpu internal cpu clock frequency -40 t a 105 c 0 16 mhz v dd1 , v dda1 operating voltages 3 (1) 1. the external power supply can be within range fr om 3 v up to 5.5 v although ic performances are optimized for power supply equal to 3.3 v. 5.5 (1) v v dd , v dda nominal operating voltages 3.3 (1) 5 (1) v out core digital power supply 1.8 (2) 2. internal core power supply voltage. c vout : capacitance of external capacitor (3) 3. care should be taken when the capacitor is select ed due to its tolerance, its dependency on temperature, dc bias and frequency. at 1 mhz 470 3300 nf esr of external capacitor (2) 0.05 0.2 ? esl of external capacitor (2) 15 nh ja (4) 4. to calculate p dmax (t a ), use the formula p dmax = (t jmax - t a )/ ja . fr4 multilayer pcb 80 c/w t a ambient temperature pd=100 mw -40 105 c table 36. operating conditions at power-up/power-down symbol parameter conditions min. (1) typ. max. (1) unit t vdd v dd rise time rate 2 s/v 1 sec/v (2) v dd fall time rate 2 s/v 1 sec/v (2) t temp reset release delay v dd rising 3 ms electrical characteristics stlux385a 72/98 docid024387 rev 2 10.3.1 vout external capacitor the stabilization of the main regulator is achieved by connecting an external capacitor cvout (a) to the vout pin. cvout is specified in the operating condition section. care should be taken to limit the series inductance to less than 15 nh. figure 12. external capacitor cvout 10.3.2 supply current characteristics the stlux385a supply current is calculated by summing the supply base current in the desired operating mode as per tab le 37 , with the peripheral supply current value reported in ta ble 39 and tab le 40 . for example, considering an application where: ? f master = f cpu = 16 mhz provided by hsi internal rc oscillator ? cpu code execution in flash ? all base peripheral actives: i 2 c, uart, dali, itc, gpio0, systimr, wwdg and iwdg ? adc conversion frequency f adc = 5.3 mhz ? acu (comparator and dac units) actives ? 6 pwm toggling @ f pwm = 0.5 mhz provided by 6 smeds running @ f smed = 12 mhz (n pwm = 6) v it + power-on reset threshold 2.65 2.8 2.98 v v it - brown-out reset threshold 2.58 2.73 2.88 v hys(bor) brown-out reset hysteresis 70 mv 1. guaranteed by design, not tested in production. 2. power supply ramp must be monotone table 36. operating conditions at power-up/power-down (continued) symbol parameter conditions min. (1) typ. max. (1) unit a. esr is the equivalent series resistance and esl is the equivalent inductance. gipd100520131002fsr esr c r leak esl docid024387 rev 2 73/98 stlux385a electrical characteristics the total current consumption is given by the following formula: where i dd(pwm) = i dd(pwm1) *n pwm more generally, the pwm current consumption has to be individually evaluated for each f smed clock grouping, using the formula below: where i = f smed clock group index; n i = pwm number of the i_th clock group; n fsmed = f smed clock group number. ic supply base current consumption the following table summarizes the current consumption measured on v dd /v dda supply pins in relevant operative conditions. i dd i dd run2 () i dd adc2 () i dd acu () i dd pll () i dd pwm () ++++ = i dd pwm i1 [] () n i ? [] i dd pwm () nfsmed i1 = ? = table 37. supply base current consumption at v dd /v dda = 3.3/5 v symbol code clock peripheral consumption (6) note op. mode code area src (2) f master f cpu periph (1,4) typ. (5) max. (5) description clock mhz mhz enable ma ma i dd(run1) flash hsi 2 2 all 2.3 2.77 reset exit condition i dd(run2) flash hsi 16 16 all 9.4 11.3 i dd(run3) ram hsi 16 16 all 4.2 5.1 i dd(run4) flash hse (1) 16 16 all 10.0 12.1 v dd /v dda = 3.3 v 10.6 12.74 v dd /v dda = 5 v i dd(run5) ram hse (5) 16 16 all 4.6 5.53 v dd /v dda = 3.3 v 5.2 6.63 v dd /v dda = 5 v i dd(slow1) flash hsi 16 2 all 3.6 4.33 i dd(slow2) ram hsi 16 2 all 2.9 3.5 i dd(slow3) flash hse (5) 16 2 all 3.9 4.7 v dd /v dda = 3.3 v 4.5 5.5 v dd /v dda = 5 v i dd(slow4) flash hsi 16 0.125 all 2.7 3.3 i dd(slow5) flash hse (5) 16 0.125 all 3.0 3.7 v dd /v dda = 3.3 v 3.6 4.4 v dd /v dda = 5 v i dd(slow6) flash lsi 0,153 0.153 all 1.5 1.9 i dd(wfi1) flash hsi 16 16 all 2.6 3.2 electrical characteristics stlux385a 74/98 docid024387 rev 2 ic low power current consumption the following table summarizes the current consumption measured on v dd /v dda supply pins in power saving conditions. i dd(wfi2) flash hse (5) 16 16 all 3.1 3.8 v dd /v dda =3.3 v 3.8 5.6 v dd /v dda =5 v 1. ?all? means: i2c, uart, dali, itc, gpio0, systimr, wwdg and iwdg peripherals active. 2. f master clock source. 3. hse frequency provided by external quartz. 4. the peripheral current consumption is supplied by the vcore voltage (1.8 v). 5. temperature operating: ta= 25 c. 6. data based on characterization results not tested in production. table 37. supply base current consumption at v dd /v dda = 3.3/5 v (continued) symbol code clock peripheral consumption (6) note table 38. supply low power consumption at v dd /v dda = 3.3/5 v symbol code clock peripheral consumption (11) note op. mode (1)(2) code area src (3) f master f cpu e 2 prom (6) mvrreg. (5) typ. (8.10) max. (9,10) description clock mhz enable enable ma ma i dd(ahlt1) flash hsi 16 enable enable 0.23 0.32 awu clocked by lsi i dd(ahlt2) flash hsi 16 enable disable 0.085 0.12 awu clocked by lsi i dd(ahlt3) flash hse (4,7) 16 enable enable 0.73 0.90 v dd /v dda =3.3 v 1.4 1.7 v dd /v dda =5 v i dd(ahlt4) flash hse (4,7) 16 enable disable 0.65 0.95 v dd /v dda =3.3 v 1.2 1.45 v dd /v dda =5 v i dd(hlt1) flash hsi 16 enable disable 0.087 0.13 i dd(hlt2) flash hse (4,7) 16 enable disable 0.075 0.11 v dd /v dda =3.3 v 0.090 0.15 v dd /v dda =5 v docid024387 rev 2 75/98 stlux385a electrical characteristics note: all the input analog signals are connected to gnd; signals of port p0, p1 and p2 are configured as input with pull-up enabled. ic peripheral current consumption (3.3 v) the following table summarizes the peripheral current consumption measured on v dd /v dda supply pins. 1. active-halt op. mode: all peripherals exc ept awu and iwdg are disabled (clock gated). 2. halt op. mode: all peripherals are disabled (clock gated). 3. f master clock source. 4. hse frequency provided by external quartz. 5. v core main dc voltage regulator. 6. e 2 prom is considered always enabled. 7. awu clocked by hse source clock. 8. temperature operating: t a = 25 c. 9. temperature operating: t a = 105 c. 10. all the analog input signals are connected to gnd; the signals of port p0, p1 and p2 are configured as input with pull-up enabled. 11. data based on characterization results not tested in production. table 39. peripheral supply current consumption at v dd /v dda = 3.3 v symbol clock peripherals consumption (9) op.mode f smed (1) f pwm (2) f adc (3) adc (7) pwm (4),(5) acu (6) typ (8) max (8) enb/dis mhz mhz mhz enb/dis num enb/di s ma ma i dd(pll) enab 0 0 0 disab 0 disab 2.26 2.7 i dd(acu) disab 0 0 0 disab 0 enab 1.89 2.27 i dd(pwm1pll96) enab 96 0.5 0 disab 1 disab 1.75 2.1 i dd(pwm6pll96) 6 10.12 12.2 i dd(pwm1pll48) enab 48 0.5 0 disab 1 disab 1.12 1.33 i dd(pwm6pll48) 6 6.54 7.85 i dd(pwm1pll24) enab 24 0.5 0 disab 1 disab 0.71 0.86 i dd(pwm6pll24) 6 4.39 5.27 i dd(pwm1pll12) enab 12 0.5 0 disab 1 disab 0.54 0.65 i dd(pwm6pll12) 63.334 i dd(pwm1pll6) enab 6 0.5 0 disab 1 disab 0.44 0.53 i dd(pwm6pll6) 62.813.4 electrical characteristics stlux385a 76/98 docid024387 rev 2 ic peripheral current consumption (5 v) the following table summarizes the peripheral current consumption measured on v dd /v dda supply pins. i dd(pwm1hsi16) enab 16 0.5 0 disab 1 disab 0.46 0.56 i dd(pwm6hsi16) 62.633.3 i dd(pwm1hsi8) enab 8 0.5 0 disab 1 disab 0.34 0.41 i dd(pwm6hsi8) 6 2.12 2.55 i dd(pwm1hsi4) enab 4 0.5 0 disab 1 disab 0.29 0.35 i dd(pwm6hsi4) 61.782.2 i dd(pwm1hsi2) enab 2 0.5 0 disab 1 disab 0.25 0.3 i dd(pwm6hsi2) 6 1.60 1.93 i dd(adc1) disab 0 0 1 enab 0 disab 1.55 1.87 i dd(adc2) disab 0 0 5.3 enab 0 disab 1.59 1.91 i dd(adc3) enab 0 0 6 enab 0 disab 1.56 1.88 1. smed frequency: - 96 mhz and 6 mhz frequencies require the pll enabled. - current table shows only a subset value of possible smed frequencies. 2. pwm frequency: - pwm toggle frequency is considered fixed to 500 khz, close to the maximum applicative value. 3. adc frequency: - 6 mhz frequency requires the pll enabled. - current table shows only a subset value of possible adc frequencies 4. number of active pwms. 5. pwm pins are loaded with a cl (load capacitance) of 50 pf. 6. if enabled all dacs and comparator units are active. 7. adc configured in circular mode. 8. temperature operating: ta= 25 c. 9. data based on characterization results not tested in production. table 39. peripheral supply current consumption at v dd /v dda = 3.3 v (continued) symbol clock peripherals consumption (9) table 40. peripheral supply current consumption at v dd /v dda = 5 v symbol clock peripherals consumption op. mode pll f smed (1) f pwm (2) f adc (3) adc (7) pwm (4,5) acu (6) typ (8) max (8) enb/dis mhz mhz mhz enb/dis num enb/dis ma ma i dd(pll) enab 0 0 0 disab 0 disab 2.32 2.78 i dd(acu) disab 0 0 0 disab 0 enab 2.22 2.66 docid024387 rev 2 77/98 stlux385a electrical characteristics pwm current consumption overview the figures that follow provide an outline view of pwm current consumption results.the consumptions are evaluated considering the maximum current at t a = 25 c with different smed operating frequencies. the charts summarize the measurements carried out from i dd(pwm1pll96) enab 96 0.5 0 disab 1 disab 1.81 2.17 i dd(pwm6pll96) 6 10.49 12.59 i dd(pwm1pll48) enab 48 0.5 0 disab 1 disab 1.18 1.42 i dd(pwm6pll48) 6 6.88 8.26 i dd(pwm1pll24) enab 24 0.5 0 disab 1 disab 0.79 0.95 i dd(pwm6pll24) 6 4.73 5.68 i dd(pwm1pll12) enab 12 0.5 0 disab 1 disab 0.58 0.7 i dd(pwm6pll12) 6 3.66 4.4 i dd(pwm1pll6) enab 6 0.5 0 disab 1 disab 0.49 0.6 i dd(pwm6pll6) 6 3.11 3.75 i dd(pwm1hsi16) enab 16 0.5 0 disab 1 disab 0.56 0.67 i dd(pwm6hsi16) 6 3.13 3.78 i dd(pwm1hsi8) enab 8 0.5 0 disab 1 disab 0.49 0.58 i dd(pwm6hsi8) 6 2.56 3.1 i dd(pwm1hsi4) enab 4 0.5 0 disab 1 disab 0.39 0.47 i dd(pwm6hsi4) 6 2.33 2.78 i dd(pwm1hsi2) enab 2 0.5 0 disab 1 disab 0.47 0.54 i dd(pwm6hsi2) 62.12.49 i dd(adc1) disab 0 0 1 enab 0 disab 2.11 2.54 i dd(adc2) disab 0 0 5.3 enab 0 disab 2.16 2.6 i dd(adc3) enab 0 0 6 enab 0 disab 2.17 2.61 1. smed frequency: - 96 mhz and 6 mhz frequencies require the pll enabled. - current table shows only a subset value of possible smed frequencies. 2. pwm frequency: - pwm toggle frequency is considered fixed to 500 khz, close to the maximum applicative value. 3. adc frequency: - 6 mhz frequency requires the pll enabled. - current table shows only a subset value of possible adc frequencies. 4. number of active pwms. 5. pwm pins are loaded with a cl (load capacitance) of 50 pf. 6. if enabled all dacs and comparator units are active. 7. adc configured in circular mode. 8. temperature operating: ta= 25 c. 9. data based on characterization results not tested in production. table 40. peripheral supply current consumption at v dd /v dda = 5 v (continued) symbol clock peripherals consumption electrical characteristics stlux385a 78/98 docid024387 rev 2 ta ble 39 and tab le 40 allowing users to derive the pwm current consumption values. figure 13. pwm current consumption with f smed =pll f pwm =0.5 mhz at v dd /v dda =3.3v figure 14. pwm current consumption with f smed =pll f pwm =0.5 mhz at v dd /v dda =5v , ' ' 3 : 0 p $ $ f w l y h 3 : 0 q x p e h u 0 + ] 0 + ] 0 + ] 0 + ] 0 + ] , ' ' 3 : 0 p $ $ f w l y h 3 : 0 q x p e h u 0 + ] 0 + ] 0 + ] 0 + ] docid024387 rev 2 79/98 stlux385a electrical characteristics figure 15. pwm current consumption with f smed =hsi f pwm =0.5 mhz at v dd /v dda =3.3v figure 16. pwm current consumption with f smed =hsi f pwm =0.5 mhz at v dd /v dda =5v 10.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a , ' ' 3 : 0 p $ $ f w l y h 3 : 0 q x p e h u 0 + ] 0 + ] 0 + ] 0 + ] , ' ' 3 : 0 p $ $ f w l y h 3 : 0 q x p e h u 0 + ] 0 + ] 0 + ] 0 + ] table 41. hse user external clock characteristics symbol parameter conditions min. max. unit f hse_ext user external clock source frequency -40 c t a 105 c 0 16 (1) mhz electrical characteristics stlux385a 80/98 docid024387 rev 2 figure 17. hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 24 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). v hseh (2) hseoscin input pin high level voltage 0.7 x v dd v dd v v hsel (2) hseoscin input pin low level voltage v ss 0.3 x v dd i leakhse (2) hseoscin input pin leakage v ss v in v dd -1 +1 a 1. in case f hse is configured as direct clock for the smed logics the maximum frequency can be 24 mhz. 2. data based on characterization results, not tested in production. table 42. hse crystal/ceramic resonator oscillator symbol parameter conditions min. typ. max. unit f hse external high speed oscillator frequency 116 (1) mhz r f feedback resistor 220 k ? c l1 , c l2 (2) recommended load capacitance (3) 20 pf i dd(hse) hse oscillator power consumption 6(startup) 2(stabilized) ma table 41. hse user external clock characteristics (continued) symbol parameter conditions min. max. unit v hseh v hsel external clock source hse oscin f hse gipd100520131400fsr docid024387 rev 2 81/98 stlux385a electrical characteristics figure 18. hse oscillator circuit diagram the crystal characteristics have to be checked with the following formula: where gm critic is calculated with the crystal parameters as follows: and where: ? rm: motional resistance (b) ? lm: motional inductance (b) ? cm: motional capacitance (b) ? co: shunt capacitance (b) ? cl1 = cl2 = c: grounded external capacitance g m oscillator transconductance 5ma/v t su(hse) (4) startup time v dd is stabilized 2.8 ms 1. in case f hse is configured as direct clock for the smed logic the maximum frequency can be 24 mhz 2. the oscillator needs two load capacitors, cl1 and cl2, to act as load for the crystal. the total load capacitance (cload) is (cl1 * cl2)/(cl1 + cl2). if cl1 = cl2, cload = cl1 / 2. some oscillators have built-in load capacitors, cl1 and cl2. 3. the oscillator selection can be optimized in terms of supply current using a high quality resonator with small rm value. 4. t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. b. refer to application crystal specification. table 42. hse crystal/ceramic resonator oscillator (continued) symbol parameter conditions min. typ. max. unit hseoscout hseoscin hseoscout gipd100520131424fsr g m g mcritic ? g mcritic 2 f hse ?? () 2r m 2c o c + () 2 ? = electrical characteristics stlux385a 82/98 docid024387 rev 2 10.3.4 internal clock sources and timing characteristics hsi rc oscillator subject to general operating conditions for v dd and t a . lsi rc oscillator subject to general operating conditions for v dd and t a . pll internal source clock table 43. hsi rc oscillator symbol parameter conditions min. (1) 1. data based on characterization results, not tested in production. typ. max. (1) unit f hsi frequency 16 mhz acc hsi accuracy of hsi oscillator (factory calibrated) (1)(2) 2. variation referred to f hsi nominal value. v dd = 3.3v t a = 25 oc -1% +1% % v dd = 3.3v -40 oc t a 105 oc -4% +4% v dd = 5v -40 oc t a 105 oc -4% +4% t su(hsi) hsi oscillator wakeup time including calibration 1 s table 44. lsi rc oscillator symbol parameter conditions min. (1) 1. guaranteed by design, not tested in production. typ. max. (1) unit f lsi frequency 153.6 khz acc lsi accuracy of lsi oscillator 3.3v v dd 5v -40 oc t a 105 oc -10% 10% % t su(lsi) lsi oscillator wakeup time 7 s table 45. pll internal source clock symbol parameter conditions min. (1) typ. max. (1) unit f in input frequency ((2) 3.3v v dd 5v -40 oc t a 105 oc 16 mhz f out output frequency 96 t lock pll lock time 200 s docid024387 rev 2 83/98 stlux385a electrical characteristics 10.3.5 memory characteristics flash program and memory/data e 2 prom memory general conditions: t a = -40 c to 105 c. 10.3.6 i/o port pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. unused input pins should not be left floating. 1. data based on characterization results, not tested in production. 2. pll maximum input frequency 16 mhz. table 46. flash program memory/data e 2 prom memory symbol parameter conditions min. (1) 1. data based on characterization results, not tested in production. typ. max. unit t prog standard programming time 66.6 ms (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) fast programming time for 1 block (128 bytes) 33.3 t erase erase time for 1 block (128 bytes) 33.3 ms n we erase/write cycles (2) (program memory) 2. the physical granularity of the memory is 4 byte s, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. t a = 25 c 10 k cycles erase/write cycles (2) (data memory) t a = 85 c 100 k t a = 105 c 35 k t ret data retention (program memory) after 10 k erase/write cycles at t a = 25 c t ret = 85 c 15 years data retention (program memory) after 10 k erase/write cycles at t a = 25 c t ret = 105 c 11 data retention (data memory) after 100 k erase/write cycles at t a = 85 c t ret = 85 c 15 data retention (data memory) after 35 k erase/write cycles at t a = 105 c t ret = 105 c 6 electrical characteristics stlux385a 84/98 docid024387 rev 2 table 47. voltage dc characteristics symbol description min. typ. max. unit v il input low voltage -0.3 0.3 * v dd v v ih input high voltage (1) 1. all signals are not 5 v tolerant (input signals can't be exceeded v ddx (v ddx = v dd , v dda )). 0.7 * v dd v dd v ol1 output low voltage @ 3.3 v (2)(3) 2. parameter applicable to signals: gpio0[5:0] (high sink selectable by high speed config.). 3. parameter applicable to signals: gpio1[5:0]/pwm[5:0]. 0.4 (13) v ol2 output low voltage @ 5 v (2)(3) 0.5 v ol3 output low voltage high sink @ 3.3 v / 5 v (1)(4)(5) 4. parameter applicable to signal: swim. 5. parameter applicable to signal: digin[0]/cco_clk 0.6 (13) v oh1 output high voltage @ 3.3 v (2)(3) v dd - 0.4 (13) v oh2 output high voltage @ 5 v (2)(3) v dd -0.5 v oh3 output high voltage high sink @ 3.3 v / 5 v (1)(4)(5) v dd - 0.6 (13 ) h vs hysteresis input voltage (6) 6. applicable to any digital inputs. 0.1 * v dd r pu pull-up resistor 30 45 60 k ? table 48. current dc characteristics symbol description min. typ. max. unit i ol1 standard output low level current @ 3.3 v and v ol1 (1)(2) 1.5 ma i ol2 standard output low level current @ 5 v and v ol2 (1)(2) 3 i olhs1 high sink output low level current @ 3.3 v and v ol3 (1)(3)(4) 5 i olhs2 high sink output low level current @ 5 v and v ol3 (1)(3)(4) 7.75 i oh1 standard output high level current @ 3.3 v and v oh1 (1)(2) 1.5 i oh2 standard output high level current @ 5 v and v olh2 (1)(2) 3 i ohhs1 high sink output high level current @ 3.3 v and v oh3 ((1)(3)(4) 5 i ohhs2 high sink output high level current @ 5 v and v oh3 (1)(3)(4) 7.75 docid024387 rev 2 85/98 stlux385a electrical characteristics 10.3.7 typical output curves the following figures show the typical output level curves measured with output on a single pin. i lkg input leakage current digital - analog v ss v in v dd (5) 1 a i_ inj injection current (6)(7) 4 ma i_ inj total injection current (sum of all i/o and control pins) (6) 20 1. parameter applicable to signals: gpio0[5:0] (high sink selectable by high speed config.). 2. parameter applicable to signals: gpio1[5:0]/pwm[5:0]. 3. parameter applicable to signal: swim. 4. parameter applicable to signal: digin[0]/cco_clk 5. applicable to any digital inputs. 6. maximum value must never be exceeded. 7. negative injection current on the adcin[7:0] signal s have to avoid since impact the adc conversion accuracy. table 49. operating frequency characteristics symbol description min. typ. max. unit f il1 digital input signal operating frequency (1)(2)(3) 1. parameter applicable to signals: gpio0[5:0] (high sink selectable by high speed config.). 2. parameter applicable to signal: swim. 3. parameter applicable to signals: digin[5:1]. 12 mhz f ih1 analog input signal operating frequency (4)(5) 4. parameter applicable to signals: gpio0[3:2] when configured as hse_oscin/oscout 5. parameter applicable to any analog signals: adcin[7:0], cpp[3:0] and cpm3. 24 f ih2 high speed input signal operating frequency (6)(7) 6. parameter applicable to signals: gpio1[5:0]/pwm[5:0]. 7. parameter applicable to signal: digin[0]/cco_clk. 128 f ol1 standard output signal operating frequency with 50 pf max. load (1) 2 f ol2 high sink output signal operating frequency with 50 pf max. load (1)(2) 10 f oh1 high speed output signal operating frequency with 50 pf max. load (6) 12 f oh2 high speed output signal operating frequency with 50 pf max. load (7) 32 table 48. current dc characteristics symbol description min. typ. max. unit electrical characteristics stlux385a 86/98 docid024387 rev 2 10.3.8 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. 10.3.9 i 2 c interface characteristics table 50. nrst pin characteristics symbol parameter conditions min. (1) 1. data based on characterization results, not tested in production. typ. max. (1) unit v il(nrst) nrst input low level voltage (1) -0.3 0.3 x v dd v v ih(nrst) nrst input high level voltage (1) 0.7 x v dd v dd + 0.3 v ol(nrst) nrst output low level voltage (1) i ol = 2 ma 0.5 r pu(nrst) nrst pull-up resistor (2) 2. the rpu pull-up equivalent resistor is based on a resistive transistor. 30 40 60 k ? t ifp(nrst) nrst input filtered pulse (3) 3. data guaranteed by design, not tested in production. 75 ns t infp(nrst) nrst not input filtered pulse (3) 500 t op(nrst) nrst output filtered pulse (3) 15 s table 51. i 2 c interface characteristics symbol parameter standard mode fast mode (1) unit min. (2) max. (2) min. (2) max. (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 0 (3) 900 (3) t r(sda) t r(scl) sda and scl rise time (v dd = 3.3 to 5 v) (4) 1000 300 t f(sda) t f(scl) sda and scl fall time (v dd = 3.3 to 5 v) (4) 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line (5) 50 50 pf 1. f master , must be at least 8 mhz to achieve maximum fast i 2 c speed (400 khz). docid024387 rev 2 87/98 stlux385a electrical characteristics 10.3.10 10-bit sar adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specified. 2. data based on standard i 2 c protocol requirement, not tested in production. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time. 4. i 2 c multifunction signals require the high sink pad configuration and the interconnection of 1 k pull-up resistances. 5. 50 pf is the maximum load capacitance value to meet the i 2 c std timing specifications. table 52. adc characteristics symbol parameter conditions min. typ. max. unit n resolution 10 bit r adcin adc input impedance 1 m ? f adc adc clock frequency 1 6 (1) 1. frequency generated selecting the pll source clock. mhz v in1 conversion voltage range for gain x1 01.25 (2)(3) 2. maximum input analog voltage cannot exceed v dda . 3. exceeding the maximum voltage on the adcin[7:0] signals for the related conversion scale must be avoided since the adc conversion accuracy can be impacted. v in2 conversion voltage range for gain x4 0 0.3125 (2)(3) v ref adc main reference voltage (4) 4. exceeding the maximum voltage on the adcin[7:0] signals for the related conversion scale must be avoided since the adc conversion accuracy can be impacted. 1.250 v t s sampling time f adc = 6 mhz 0.50 s t stab wakeup time from adc standby 30 t conv1 single conversion time including sampling time f adc = 6 mhz 2.42 t conv2 continuous conversion time including sampling time f adc = 6 mhz 3 electrical characteristics stlux385a 88/98 docid024387 rev 2 adc accuracy characteristics at v dd /v dda 3.3 v table 53. adc accuracy characteristics at v dd /v dda 3.3 v symbol parameter conditions (1) 1. measured with rain<10 k (rain external series resistance interconnected between the ac signal generator and the adc input pin). typ. (2) 2. temperature operating: t a = 25 c. min. (3) 3. data based on characterization results, not tested in production. max. (3) unit |e t | total unadjusted error (4)(5)(6) 4. adc accuracy vs. negative injection current. injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. it is recommended a schottky diode (pin to ground) to be added to standard analog pins which may potentially inject the negative current. any positive in jection current within the limits specified for i inj(pin) and iinj(pin) in the i/o port pin characteristic section does not affect the adc accuracy. the adc accuracy parameters may be also impacted exceeding the adc maximum input voltage v in1 or v in2 . 5. results in manufacturing test mode. 6. data aligned with trimming voltage parameters. f adc = 6 mhz gain 1 2.8 lsb |e o |offset error (4)(5)(6) 0.3 |eg| gain error (4)(5)(6)(7) 7. gain error evaluation with two point method. 0.4 e o+g offset + gain error (7)(8) 8. temperature operating range: 0 oc t a 85 oc. -8.5 9.3 e o+g offset + gain error (7)(9) 9. temperature operating range: -25 oc t a 105 oc. -11 11 e o+g offset + gain error (7)(10) 10. temperature operating range: -40 oc t a 105 oc. -14.3 11.3 |ed| differential linearity error (2,3,4) 0.5 |e l | integral linearity error (4)(5)(6) 1.4 |e t | total unadjusted error ((4)(5)(6) f adc = 6 mhz gain 4 2.8 |e o |offset error (4)(5)(6) 0.3 |e g | gain error (4)(5)(6)(7) 0.4 e o+g offset + gain error (7)(8) -12.7 15.5 e o+g offset + gain error (5)(9) -16.7 18.8 e o+g offset + gain error (7)(10) -19.2 18.8 |e d | differential linearity error (4)(5)(6) 0.5 |e l | integral linearity error (4)(5)(6) 1.4 docid024387 rev 2 89/98 stlux385a electrical characteristics adc accuracy characteristics at v dd /v dda 5 v table 54. adc accuracy characteristics at v dd /v dda 5 v symbol parameter conditions (1) 1. measured with rain<10 k (rain external series resistance interconnected between the ac signal generator and the adc input pin). typ. (2) 2. temperature operating: t a = 25 c. min. (3) 3. data based on characterization results, not tested in production. max. (3) unit |e t | total unadjusted error (4)(5)(6) 4. adc accuracy vs. negative injection current. injecting negative current on any of the analog input pins should be avoided as this reduces the accuracy of the conversion being performed on another analog input. it is recommended a schottky diode (pin to ground) to be to added to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and iinj(pin) in the i/o port pin characteristic section does not affect the adc accuracy. the adc accuracy parameters may be also impacted exceeding the adc maximum input voltage v in1 or v in2 . 5. results in manufacturing test mode. 6. data aligned with trimming voltage parameters. f adc = 6 mhz gain 1 tbd lsb |e o | offset error (4)(5)(6) 0.5 |e g | gain error (4)(5)(6)(7) 7. gain error evaluation with two point method. 0.4 e o+g offset + gain error (7)(8) 8. temperature operating range: 0 oc t a 85 oc. -8.3 8.9 e o+g offset + gain error (7)(9) 9. temperature operating range: -25 oc t a 105 oc. -10.9 10.9 e o+g offset + gain error (7)(10) 10. temperature operating range: -40 oc t a 105 oc. -13.8 10.9 |e d | differential linearity error (2,3,4) 0.8 |e l | integral linearity error (4)(5)(6) 2.0 |e t | total unadjusted error ((4)(5)(6) f adc = 6 mhz gain 4 tbd |e o | offset error (4)(5)(6) 1.2 |e g | gain error (4)(5)(6)(7) 0.2 e o+g offset + gain error (7)(8) -12.2 15.3 e o+g offset + gain error (5)(9) -16.4 18.5 e o+g offset + gain error (7)(10) -18.8 18.5 |ed| differential linearity error (4)(5)(6) 0.8 |e l | integral linearity error (4)(5)(6) 2.0 electrical characteristics stlux385a 90/98 docid024387 rev 2 10.3.11 analog comparator characteristics 10.3.12 dac characteristics where: ? v fullscale = v fullscale (sample, t) ? v offset = v offset (sample, t) ? inl = inl(sample, n) table 55. analog comparator characteristics symbol parameter conditions min. (1) 1. data based on characterization results, not tested in production. typ. max. (1) unit v in comparator input voltage range -40 oc t a 105 oc 01.23 (2) 2. maximum analog input voltage cannot exceed v dda . v v icpm3 comparator 3 external input voltage range 01.23 (2)(3) 3. the comparator 3 can be configured with the external reference voltage signal cpm3. v v offset comparator offset error 15 mv t comp comparison delay time 50 ns table 56. dac characteristics symbol parameter conditions min. (1) 1. data based on characterization results, not tested in production. typ. max. (1) unit v full scale dac full scale -40 oc t a 105 oc 1.2 1.26 v v offset dac offset 4 mv v dac dac out voltage v offset v full scale mv lsb 82 mv inl integral non linearity 0.12 lsb n[0,15]:vdac(n) v fullscale v offset ? () 15 --------------------------------------------------- - n () v offset + = n[1-14]:vdac(n) v fullscale v offset ? () 15 --------------------------------------------------- - ninl + () v offset + = docid024387 rev 2 91/98 stlux385a electrical characteristics 10.4 emc characteristics 10.4.1 electrostatic discharge (esd) electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). 10.4.2 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. table 57. esd absolute maximum ratings symbol ratings conditions maximum value unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25 c, conforming to jedec/jesd22-a114e 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25 c, conforming to ansi/esd stm 5.3.1 esda 500 v esd(mm) electrostatic discharge voltage (machine model) t a = 25 c, conforming to jedec/jesd-a115-a 200 table 58. electrical sensitivity symbol parameter conditions level lu static latch-up class t a = 105 c a thermal characteristics stlux385a 92/98 docid024387 rev 2 11 thermal characteristics the stlux385a functionality cannot be guaranteed when the device is operating under the maximum chip junction temperature (t jmax ). t jmax , in degrees celsius, may be calculated using the following equation: where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + pi/o max ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level. table 59. package thermal characteristics symbol parameter value unit ja thermal resistance junction-to-ambient (1) 1. thermal resistance are based on jedec jesd51-2 with 4-layer pcb in a natural convection environment. 80 c/w t jmax t amax pd max ja () + = docid024387 rev 2 93/98 stlux385a package mechanical data 12 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 60. tssop38 mechanical data dim. mm min. typ. max. a 1.20 a1 0.05 0.15 a2 0.80 1.00 1.05 b0.17 0.27 c0.09 0.20 d 9.60 9.70 9.80 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e0.50 l 0.45 0.60 0.75 l1 1.00 k0 8 aaa 0.10 package mechanical data stlux385a 94/98 docid024387 rev 2 figure 19. tssop8 package drawing 0117861_c docid024387 rev 2 95/98 stlux385a stlux385a development tools 13 stlux385a development tools the development tool for the stlux385a microcontroller is provided by raisonance with the c compiler and the integrated development environment (ride7), which provides start-to- finish control of application development including code editing, compilation, optimization and debugging. the hardware tool includes the rlink in-circuit debugger/programmer (usb/jtag). order codes stlux385a 96/98 docid024387 rev 2 14 order codes table 61. ordering information order code package packaging stlux385a tssop38 tube STLUX385ATR tape and reel docid024387 rev 2 97/98 stlux385a revision history 15 revision history table 62. document revision history date revision changes 04-apr-2013 1 initial release. 06-jun-2013 2 document status promoted from preliminary to production data. stlux385a 98/98 docid024387 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: stmicroelectronics: ? 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